--(BUSINESS WIRE)--RISC-V Foundation:
WHERE: Hall 3A, booth 3A-419, NürnbergMesse, Messezentrum 1, 90471 Nürnberg, Germany
WHEN: Tuesday, Feb. 27 – Thursday, March 1, 2018
WHAT: The RISC-V Foundation will share updates on new products and implementations from its expansive membership at Embedded World 2018. The Foundation will be exhibiting at hall 3A, booth 3A-419. The RISC-V Foundation booth will include pods from member companies Antmicro, GreenWaves Technologies, Imperas, Syntacore, UltraSoC and VectorBlox.
Embedded World invited the Foundation to host a full-day RISC-V track on Tuesday, Feb. 27. The speaking track, called RISC-V Class, will feature 10 half hour presentations from member companies, universities and the Foundation. During the RISC-V track, speakers will discuss the role of the RISC-V ecosystem in advancing innovation and growth in the semiconductor and embedded systems industries. Speaking sessions include:
Running RTOS on RISC-V
- When: 9:30 a.m. – 10 a.m. CET
- Who: Tim Morin, Microsemi Corporation
RISC-V: Emulation and Rich, Non-Intrusive Analytics Address
- When: 10 a.m. – 10:30 a.m. CET
- Who: Rupert Baines, UltraSoC and Russ Klein, Mentor Graphics
Cycle Approximate Timing Simulation of RISC-V Processors
- When: 10:30 a.m. – 11 a.m. CET
- Who: Lee Moore, Imperas
Securing RISC-V Machines Dynamically with Hardware-Enforced
- When: 11:30 a.m. – 12 p.m. CET
- Who: Steven Milburn, Dover Microsystems
RISC-V ISA and Foundation Overview
- When: Noon – 12:30 p.m. CET
- Who: Rick O’Connor, RISC-V Foundation
A RISC V-Based Open Hardware Platform for Wearable
- When: 2:30 p.m. – 3 p.m. CET
- Who: Stefan Mach, ETH Zurich
A RISC-V Based Heterogeneous Cluster
- When: 3 p.m. – 3:30 p.m. CET
- Who: Davide Rossi, University of Bologna
Precisely Engineered RISC-V Embedded Processors in 30 Days
- When: 4 p.m. – 4:30 p.m. CET
- Who: Keith Graham, University of Colorado Boulder
RISC-V in High Computing, Ultra-Low-Power, Programmable Circuits
- When: 4:30 p.m. – 5 p.m. CET
- Who: Eric Flamand, GreenWaves Technologies
Efficiency of the RISC-V ISA-Level Custom Extension
- When: 5 p.m. – 5:30 p.m. CET
- Who: Grigory Okhotnikov, Syntacore
Throughout the show Microsemi will be hosting sessions at its booth, located at Hall 1/ 1-431, to discuss Microsemi's Mi-V RISC-V ecosystem. RISC-V Foundation Executive Director Rick O'Connor will also be a featured speaker at the booth, presenting an overview of the RISC-V Foundation and the ISA.
To learn more about the activities of the RISC-V Foundation and its member companies at Embedded World, please visit: https://riscv.org/2018/01/risc-v-embeddedworld-2018/.
To schedule a meeting with RISC-V or a member organization, please email: email@example.com. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.