ASE Expands PowerSiP™ Platform for Next-Generation AI Power Delivery

Vertically integrated 3D SiP modules shorten high-current transmissions path, reducing parasitic routing losses by 50% or more to enhance system efficiency

SUNNYVALE, Calif.--(BUSINESS WIRE)--Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711) and a leading provider of semiconductor assembly and test services, today announced the expansion of its PowerSiP™ platform with a 3D System-in-Package (SiP) solution designed to enable vertically integrated voltage regulator modules (VRMs) for higher system efficiency in AI data center and high-performance computing applications. Available now, the solution combines qualified assembly technologies and a sub-module toolbox to support miniaturized, highly integrated, and thin VRMs for vertical board-to-chip power delivery. By bringing voltage regulation closer to the processor, the vertical architecture can cut parasitic routing losses by 50% or more, helping improve overall system efficiency as AI compute power requirements continue to rise.

As AI processors continue to scale in performance, their energy requirements are increasing significantly, making efficient power delivery a critical system-level challenge. Today’s high-performance AI SoCs can exceed kilowatt-level power and require peak currents greater than 1,000 amps at sub-volt levels. At these currents, traditional lateral architectures can introduce significant routing losses as electricity travels across the PCB, through package substrates and interconnects before reaching the processor. Reducing the distance between voltage regulation and the processor is therefore becoming increasingly important to minimize losses and improve overall system efficiency.

ASE’s PowerSiP™ vertical integration toolbox includes double-sided connected capacitors sandwiched between coreless substrates; substrate-less, solder-free cap array modules with exposed terminals for embedded substrate or PCB solutions; high-aspect-ratio 4:1 copper pin integration for lower packaging impedance; and high-density active and passive component integration using single- or double-sided molding. Together, these capabilities address the density and thickness constraints associated with placing voltage regulation on the back side of the PCB in space-constrained compute trays.

“Power efficiency is becoming a defining challenge for next-generation AI systems,” said Dr. Harrison Chang, Vice President of Corporate Research and Development at ASE. “By shortening the high-current transmission path, our vertically integrated PowerSiP™ solution can reduce parasitic routing losses by 50% or more, translating directly into meaningful power savings at the system level.”

“AI systems are placing unprecedented demands on board-to-chip power delivery, making the final stage of voltage regulation increasingly important,” said Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE. “PowerSiP™ brings together advanced packaging and integration technologies that enable compact, high-density voltage regulation to be positioned directly beneath the processor, addressing the stringent space and performance requirements of next-generation AI systems.”

“As AI infrastructure evolves toward increasingly heterogeneous and modular compute architectures, system-level power efficiency will become even more critical. The expansion of PowerSiP™ reflects ASE’s focus on packaging innovation that addresses broader system-level power challenges,” said Yin Chang, Executive Vice President at ASE. “Our qualified assembly technologies provide customers with a flexible toolbox for building compact, highly integrated VRMs that can be vertically integrated for next-generation GPUs, TPUs and custom ASICs in AI data center and HPC applications.”

ASE will participate at SEMICON West 2026 in San Francisco, from October 13 to October 15, where Executive Vice President Yin Chang will deliver the Advanced Packaging Heterogeneous Integration Summit keynote titled “The Architecture of Intelligence: Advanced Packaging for AI at Scale.” Simultaneously, ASE will participate at OCP 2026 in San Jose, from October 13 to October 15, where Corporate Vice President Dr. CP Hung will participate on a panel in the Open Chiplet Economy session, discussing “Physical AI – Addressing the barriers to interoperable chiplets in automotive and robotics.”

Supporting resources

• For more, please visit: https://ase.aseglobal.com/powersip
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About ASE, Inc.

ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test. Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, Automotive, 5G, High-Performance Computing, and more. To learn about our advances in SiP, Fanout, MEMS & Sensor, Flip Chip, and 2.5D, 3D & TSV technologies, all ultimately geared towards applications to improve lifestyle and efficiency, please visit: aseglobal.com or follow us on LinkedIn & X: @aseglobal.