ASE Launches Automated 310mm Panel-Level Packaging to Accelerate AI Innovation

Driving performance, scalability, and efficiency for next-generation compute workloads

SUNNYVALE, Calif.--(BUSINESS WIRE)--Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711) and a leading provider of semiconductor assembly and test services, today announced the development of an industry-first automated 310mm × 310mm panel-level packaging production line, advancing its leadership in next-generation advanced packaging technologies. This milestone expands economies of scale by enabling a seamless transition from wafer-level packaging to panel-level packaging while preserving design rule consistency across FOCoS and FOCoS-Bridge packaging platforms. The new panel line is expected to enter production in the first half of 2027.

The announcement further accentuates ASE’s commitment to enabling the semiconductor industry’s transition into the era of heterogeneous integration, where performance is increasingly defined by high-bandwidth, low-latency interconnects across chiplets, ASICs, and high-bandwidth memory (HBM). As AI accelerators and high-performance computing (HPC) devices grow in complexity, panel-level packaging represents a critical innovation to support the roadmap toward trillion-transistor system-in-package architectures.

ASE’s automated panel-level packaging line supports 310mm × 310mm format and is compatible with advanced packaging platforms including FOCoS and FOCoS-Bridge, delivering line/space capabilities of 2/2µm and 8/8µm, respectively. By transitioning from traditional round wafers to rectangular panels, ASE enables significantly greater usable area—up to 96,100 mm² per panel—allowing for more dies per unit and improved material efficiency.

This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency. The larger panel format supports higher throughput and reduced cycle time, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC applications, where demand for larger package sizes and higher I/O density continues to accelerate.

“ASE is driving a fundamental shift in advanced packaging by introducing an automated panel-level manufacturing platform that significantly improves scalability and efficiency,” said Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE. “This innovation enables higher integration density and supports the evolving requirements of AI and HPC systems, where performance, power efficiency, and manufacturability must be addressed holistically.”

The panel-level platform delivers higher throughput through large-area processing and reduced tool change steps, while offering a flexible foundation for heterogeneous integration and system-in-package (SiP) solutions. It supports a wide range of applications including AI, HPC, networking, high-end gaming, and edge AI, helping customers meet performance targets with greater manufacturing efficiency and faster time-to-market.

“Panel-level packaging represents a pivotal step in enabling the next wave of AI-driven innovation,” said Yin Chang, Executive Vice President at ASE. “As AI training and inference workloads scale, achieving the highest levels of system performance requires not only advanced silicon, but also advances in packaging efficiency and integration. Our panel-level platform enhances throughput, optimizes material utilization, and delivers the scalability needed for increasingly complex computing architectures across a broad range of applications, with hyperscale customers continuing to drive the pace of innovation.”

ASE’s new solution also reinforces its competitive differentiation through faster cycle times, scalable manufacturing, and alignment with long-term industry roadmaps for chiplet-based architectures and large-form-factor integration. As the industry moves beyond the limitations of traditional wafer-based processes, ASE continues to lead in delivering advanced packaging solutions that enable new levels of system performance and efficiency.

ASE will participate in the 76th IEEE Electronic Components and Technology Conference (ECTC) in Orlando, Florida, from May 26 to May 29, 2026. Dr. Tien Wu, ASE’s Chief Executive Officer, will deliver the plenary keynote titled “Advanced Packaging & the Future of System Optimization.” Executive Vice President Yin Chang and Corporate Vice President Dr. C. P. Hung will also participate in special panel sessions, covering “Enabling Next-Generation Advanced Packaging Technology – From Wafer to Panel” and “Co-Design in High-Performance Packaging,” respectively.

Supporting resources

• For more, please visit: https://ase.aseglobal.com/310x310
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About ASE, Inc.

ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test. Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, Automotive, 5G, High-Performance Computing, and more. To learn about our advances in SiP, Fanout, MEMS & Sensor, Flip Chip, and 2.5D, 3D & TSV technologies, all ultimately geared towards applications to improve lifestyle and efficiency, please visit: aseglobal.com or follow us on LinkedIn & X: @aseglobal.