Ceremorphic Exits Stealth Mode; Unveils Technology Plans to Deliver a New Architecture Specifically Designed for Reliable Performance Computing

Complete Silicon System Addresses Today’s Critical Computing Challenges Around Reliability, Security, Energy Efficiency, and Scalability

Key Highlights:

• Funded by Ceremorphic founders in $50 million Series A round
• R&D spanning over 5 years and backed by more than 100 patents in core technologies
• Company’s first chip QS 1, in Hierarchical Learning Processor™ series, is designed in TSMC 5nm process node
• Employs 150 employees with plans to grow to 250 in 2022
• Led by proven Management Team, Board of Directors and Advisors
• Headquartered in Silicon Valley with a development center in India

SAN JOSE, Calif.--(BUSINESS WIRE)--Armed with more than 100 patents and leveraging multi-decade expertise in creating industry-leading silicon systems, Ceremorphic® Inc. today announced its plans to deliver a complete silicon system that provides the performance needed for next-generation applications such as AI model training, HPC, automotive processing, drug discovery, and metaverse processing. Designed in advanced silicon geometry (TSMC 5nm node), this new architecture was built from the ground up to solve today’s high-performance computing problems in reliability, security and energy consumption to serve all performance-demanding market segments.

Ceremorphic was founded in April 2020 by industry-veteran Dr. Venkat Mattela, the Founding CEO of Redpine Signals, which sold its wireless assets to Silicon Labs, Inc. in March 2020 for $308 million. Under his leadership, the team at Redpine Signals delivered breakthrough innovations and industry-first products that led to the development of an ultra-low-power wireless solution that outperformed products from industry giants in the wireless space by as much as 26 times on energy consumption. Ceremorphic leverages its own patented multi-thread processor technology ThreadArch® combined with cutting-edge new technology developed by the silicon, algorithm and software engineers currently employed by Ceremorphic. This team is leveraging its deep expertise and patented technology to design an ultra-low-power training supercomputing chip.

“Having developed many innovations in multi-thread processing, algorithm driven VLSI, reliable performance circuits, low-energy interface circuits, quantum resistant security microarchitecture, and new device architectures beyond CMOS, Ceremorphic is well on its way to accomplish our goals,” said Venkat Mattela, Founder and CEO of Ceremorphic. “The challenges this market faces with ‘reliable performance computing’ cannot be solved with existing architectures, but rather needs a completely new architecture built specifically to provide reliability, security, energy efficiency, and scalability.”

Added Mattela, “We strongly believe that building a technology foundation is key to developing highly differentiated products that can lead the industry. We proved that in the wireless space with Redpine Signals and we are now doing the same thing in the computing space with Ceremorphic.”

“I am very impressed with the Ceremorphic approach to solving some of the key challenges in the reliability and performance computing space today,” said Subhasish Mitra, Professor of Electrical Engineering and of Computer Science at Stanford University. “Reliable performance computing is absolutely something this industry needs and the approach that Ceremorphic is pursuing is a significant step in the right direction.”

Hierarchical Learning Processor (HLP) deploys the right processing system for optimal power performance operation. Key features of the QS 1 include the following:

• Custom Machine Learning Processor (MLP) running at 2GHz
• Custom FPU running at 2GHz
• Patented Multi-thread processing macro-architecture, ThreadArch® based RISC –V® processor for proxy processing (1GHz)
• Custom video engines for Metaverse Processing (1GHz) along with M55 v1 core from ARM®
• Custom designed X16 PCIe 6. 0 / CXL 3.0 connectivity interface
• Open AI framework software support with optimized compiler and application libraries
• Soft error rate: (100,000)^-1

The Ceremorphic architecture has been designed to scale across multiple compute intensive markets and applications, including AI training supercomputing, data center processing, automotive, metaverse processing, robotics and life sciences. For more information on each application area, visit the Ceremorphic applications webpage at this link.

About Ceremorphic

Founded in April 2020, Ceremorphic currently has 150 full-time employees dedicated to developing advanced silicon and software products for next-generation computing systems. Leveraging more than 100 patents and proven expertise in creating industry-leading silicon system products, Ceremorphic has built a new architecture that delivers the performance needed for applications such as AI model training, automotive processing, drug discovery, HPC, and metaverse processing with unprecedented energy efficiency and reliability. Designed in advanced silicon technology node (TSMC 5nm), this architecture solves today’s high-performance computing problems in reliability, security and energy consumption across all performance-demanding market segments. For more information, visit https://www.ceremorphic.com.

Copyright 2022. All rights reserved. Ceremorphic and ThreadArch are registered trademarks and Reliable Performance Computing and Hierarchical Learning Processor are trademarks of Ceremorphic, Inc. All other trademarks are the property of their respective owners.