MIPS I8500 Processor Orchestrates Data Movement for the AI Era

MIPS I8500 delivers deterministic, secure data orchestration for Physical AI with 3rd generation four-thread-per-core processor built using open RISC-V ISA

SAN JOSE, Calif.--(BUSINESS WIRE)--MIPS, a GlobalFoundries company, announced today the MIPS I8500 processor is now sampling to lead customers. Featured at GlobalFoundries’ Technology Summit in Munich, Germany today, the I8500 represents a class of intelligent data movement processor IP designed for real-time, event-driven computing platforms. Targeting hyperscale, storage, automotive, industrial, and communications infrastructure markets, the I8500 is built to meet the demands of the AI supercycle and the rise of Physical AI.

“As AI moves beyond the datacenter into physical environments, platforms require real-time data orchestration capabilities far beyond what traditional processors can deliver,” said Sameer Wasson, MIPS CEO. “The I8500 marks the evolution of our proven data movement architecture into the open RISC-V era, delivering performance, efficiency, and design freedom for next-generation Physical AI solutions.”

The MIPS I8500 features a scalable multithreaded architecture with 4 threads per core and support for multi-cluster deployments, enabling up to 24 threads per cluster. It delivers ultra-low-latency, deterministic data movement with integrated security, ideal for orchestrating packet flows across accelerators and enabling intelligent communication between compute blocks, humans, and networks. Its energy-efficient design ensures optimal performance for edge AI workloads, while RVA23 profile readiness and support for Linux and Real-Time operating systems ensures software portability and ecosystem alignment.

“The MIPS I8500 is a timely and strategic advancement for embedded and edge computing,” said Steven Dickens, CEO & Founder at HyperFRAME Research. “The combination of scalable multithreading, deterministic performance, and secure data orchestration directly addresses the growing demand for real-time, event-driven processing in markets like automotive, industrial automation, and communications infrastructure. MIPS is clearly positioning itself as a leader in enabling Physical AI at the silicon level.”

Example Applications of the MIPS I8500 processor:

• Data Orchestration at High Speed: Fast rule-based packet classification essential for Smart NICs, DPUs and backhaul processors in data centers and telecom networks.
• Industrial IoT & Automation Ready: Fast, local protocol and routing processing for workloads that need real-time control, prioritization, and secure processing.
• Secure, Scalable Data Movement: Provides deterministic data handling critical for predictive maintenance and AI-driven diagnostics.
• Scalable Architecture: Flexible deployment in 5G/6G and edge computing environments for optimal performance with multi-core, multi-cluster design offerings.
• Dynamic management, encryption, & QoS: Enable dynamic traffic management, encryption, and QoS to maintain secure communication channels with programmable pipelines.

Customer evaluation of the MIPS I8500 Atlas Explorer Core Model is now available, enabling software-hardware co-design to accelerate design cycles and speed up time to market. Visit MIPS at the RISC-V Summit North America on October 22-23, or Contact Us.

About MIPS

MIPS, a GlobalFoundries company, develops processor IP for edge and embedded computing platforms at foundry scale. With a 40-year heritage in RISC computing innovation and safety capable processing, MIPS is uniquely positioned to advance Physical AI in industrial robotics, automotive applications, and more. MIPS technology is based on the open, modular RISC-V instruction set architecture. For more information, please visit MIPS.com.