CAMBRIDGE, England & SANTA CLARA, Calif.--(BUSINESS WIRE)--Blueshift Memory, designer of a novel proprietary high-speed memory architecture, has announced that the Cambridge Architecture™ has been selected to receive the Most Innovative Memory Technology award in the Memory Accelerator Architecture category at last week’s Flash Memory Summit Best in Show Awards in Santa Clara – the world’s largest computer memory event.
“Data transfer between core and memory has become the limiting factor in computational speed. AI and Big Data applications need to deal with large data sets, which only intensifies the need for a next generation architecture,” said Jay Kramer, Chairman of the Awards Program and President of Network Storage Advisors Inc. “We are proud to recognize Blueshift Memory for the innovation of Cambridge Architecture™. This technology provides a new level of computational efficiency with zero latency and up to 1000 times faster memory access, while providing up to a 50% reduction in energy consumption by eliminating unnecessary movement of data.”
“It is an incredible accolade that the industry experts at the world’s largest memory show have selected Blueshift Memory for this award,” said Peter Marosan, CTO and founder of Blueshift Memory. “We have worked extremely hard over the past couple of years to prove the concept of our disruptive non-Von Neumann architecture and to develop our self-optimizing memory solution, and it is very rewarding to have our efforts acknowledged by the Flash Memory Summit Awards Program.”
“Our first Flash Memory Summit has been a huge success for the company,” said Helen Duncan, Chief Marketing Officer of Blueshift Memory. “We have made some great connections among the delegates we’ve met here, and the quality of the technical presentations has been outstanding.”
In a presentation at the Summit, Sarmad Adeel of Blueshift Memory described the Innovate UK-funded development of an accelerator chip for computer vision (CV) AI-enhanced image recognition. The paper, entitled ‘Novel memory-efficient computer architecture integration in RISC-V with CXL’ reported that this demonstration device had achieved an acceleration factor of 16 to 128 times for processing image data, along with ultra-low power consumption. Work is now continuing on realizing the full potential of the architecture in big data applications, and on applying quantum resilient data protection to the chip design.