-

Cadence Announces Full DRAM Verification Solution for Automotive, Data Center, and Mobile Applications

Highlights:

  • New solution accelerates IP-to-SoC-level verification for complex memory controllers, PHYs and devices for LPDDR5x, DDR5, HBM3 and GDDR6 protocols
  • Up to 10X increase in verification throughput enables total IP-to-SoC-level verification of advanced designs with multiple DDR interfaces

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a new DRAM verification solution, allowing customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. Using the full DRAM verification solution, which delivers up to 10X increased verification throughput, customers can quickly and effectively perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces.

Modern SoC designs leverage advanced memory technologies, such as LPDDR5x, DDR5, HBM3 and GDDR6, which require rigorous verification at the PHY and IP levels to ensure compliance with the JEDEC standard as well as SoC-level verification to meet application-specific system performance definitions and data and cache coherency requirements.

“DRAM memory verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” said Paul Cunningham, senior vice president and general manager, R&D, in the System & Verification Group at Cadence. “With the industry’s first full DRAM verification solution, we’re enabling our customers to verify their IP designs effectively and ensure their designs comply with the JEDEC standard specification as well as the memory subsystem application-specific performance metrics to provide the fastest path to IP and system verification closure.”

The new DRAM verification solution enables IP-level verification through Cadence® PHY VIPs and memory models with a direct and seamless path to SoC-level verification with the Cadence System VIP solution, including the System Performance Analyzer, System Traffic Libraries and System Scoreboard, all with built-in integration and content for DRAM interfaces, enabling fast and efficient memory subsystem and SoC verification for simulation and emulation environments.

The solution also includes Cadence TripleCheck technology, which provides users with a verification plan linked to a specification, including JEDEC, DFI and PHY, comprehensive coverage models, and a test suite to ensure compliance with the interface specification.

“Micron is committed to leading the development of next-generation memory technologies that drive value from the data center to the intelligent edge and across client and mobile user experiences,” said Malcolm Humphrey, vice president and general manager of the Compute DRAM Products Group at Micron. “Our collaboration with Cadence accelerates ecosystem development to deliver innovative memory solutions.”

The new verification solution for DRAM verification is part of the broader Cadence verification full flow, which includes Palladium® Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper® Formal Verification Platform, the Helium Virtual and Hybrid Studio, and the vManager Verification Management Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The DRAM verification solution and verification full flow support the company’s Intelligent System Design strategy, enabling SoC design excellence. For more information, please visit www.cadence.com/go/DRAMVerification.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc.

Category: Featured

Contacts

Cadence Newsroom
408-944-7039
newsroom@cadence.com

Cadence Design Systems, Inc.

NASDAQ:CDNS
Details
Headquarters: San Jose, California
CEO: Anirudh Devgan
Employees: 12700
Organization: PUB
Revenues: 4.641 Billion (2024)
Net Income: 1.055 Billion (2024)

Release Summary
Cadence announced a new DRAM verification solution, allowing customers to optimize SoC designs for data center, consumer, and automotive applications.
Release Versions

Contacts

Cadence Newsroom
408-944-7039
newsroom@cadence.com

More News From Cadence Design Systems, Inc.

Cadence Tensilica IP Powers Analog Devices’ Next-Generation DSP Architecture

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced that its Tensilica IP Group and Analog Devices, Inc. (ADI) worked together to develop the latest generation of SHARC® automotive audio processors, further strengthening ADI’s industry-leading position in premium in-vehicle audio solutions. The joint effort brings Cadence’s highly optimized Tensilica DSP architecture into the next-generation ADSP product family from ADI, enabling richer audio experiences, enhanced voice in...

Cadence’s Anirudh Devgan to Present at Goldman Sachs Communacopia + Technology Conference

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence’s Anirudh Devgan to Present at Goldman Sachs Communacopia + Technology Conference...

Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express® (PCIe®) 6.0 specification, implemented in the TSMC N3 process, achieved first-pass success at the recent PCI-SIG® compliance workshop held in late July. The workshop marked the industry’s first official event for PCIe 6.0 specification compliance testing, with Cadence’s x8 subsystem solution tested at the full PCIe 6.0 specification speed of 64 GT/s. The complete Cadence...
Back to Newsroom