-

Cadence Collaborates with GlobalFoundries® to Qualify Pegasus Verification System for 12LP/12LP+ and 22FDX™ Technologies

Pegasus Verification System qualification enables customers to confidently perform physical verification for hyperscale, aerospace 5G communications, consumer and automotive designs

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® Pegasus™ Verification System is now qualified for the GlobalFoundries® (GF®) 12LP/12LP+ and 22FDX™ technologies. The collaboration with GF confirmed that the Pegasus Verification System meets the rigorous accuracy and runtime targets customers have come to expect with physical verification for these advanced GF nodes. GF-qualified rule decks are now available to help customers who are designing and taping out hyperscale, aerospace, 5G communications, consumer and automotive applications ramp up quickly.

The Pegasus Verification System offers several benefits to customers designing on GF 12LP/12LP+ and 22FDX technologies. Architected from the ground up to provide massively scalable runs, the Pegasus Verification System provides fast turnaround times and more predictable design cycle times with design rule checks (DRC), layout versus schematic (LVS), metal fill and design-for-manufacturing (DFM) . It features tight in-design integration with Cadence’s Innovus™ Implementation System and Virtuoso® platform, providing improved productivity and checks throughout the implementation flow. Also, designers can easily fulfill mandatory DFM requirements by leveraging integrated hotspot detection with seamless automated fixing. For more information on the Pegasus Verification System, please visit www.cadence.com/go/pegasusgfpr.

“Our collaboration with Cadence helps ensure that customers can use the qualified Pegasus Verification System to create high-quality designs in high-growth markets using our 12LP/12LP+ and 22FDX platforms,” said Richard Trihy, vice president of customer design enablement at GF. “Through the availability of the collateral, we’re also giving customers a fast path to adoption so they can quickly start reaping the benefits of our technologies.”

“Cadence and GF worked together on the Pegasus Verification System qualification to provide customers with added confidence that they can achieve DRC, LVS, metal fill and mandatory DFM requirements on GF’s advanced technologies and get to market faster,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “The Pegasus Verification System provides customers with a compelling offering, given its massive scalability and tight integration with Innovus Implementation and the Virtuoso platform, providing faster physical verification cycles and shorter iterations, which enables them to stay in front of the competition.”

The Pegasus Verification System is part of the broader Cadence digital full flow, which provides optimal power, performance and area (PPA) with a faster path to design closure and supports Cadence’s Intelligent System Design™ strategy, enabling SoC design excellence.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Category: Featured

Contacts

Cadence Newsroom
408-944-7039
newsroom@cadence.com

Cadence Design Systems, Inc.

NASDAQ:CDNS
Details
Headquarters: San Jose, California
CEO: Anirudh Devgan
Employees: 12700
Organization: PUB
Revenues: 4.641 Billion (2024)
Net Income: 1.055 Billion (2024)

Release Summary
The Cadence Pegasus Verification System is now qualified for the GlobalFoundries (GF) 12LP/12LP+ and 22FDX technologies.
Release Versions

Contacts

Cadence Newsroom
408-944-7039
newsroom@cadence.com

More News From Cadence Design Systems, Inc.

Cadence Collaborates With TSMC to Deliver Certified Tool Solutions and Industry-Leading, Silicon-Proven UALink IP on TSMC Advanced Processes

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced an expanded partnership with TSMC to deliver advanced capabilities for AI and HPC designers. Cadence has achieved tool certification for TSMC’s advanced A14 process, demonstrated an industry-leading UALink solution in TSMC N3P, and introduced new silicon-proven IP for N3P and N2P technologies. Through this partnership, the companies are enabling agentic AI chip and 3D-IC design flows across TSMC's N3, N2, A16™ and A14 pro...

Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today introduced a new agent for Cadence® ChipStack™ AI Super Agent that automates front‑end digital design and verification—covering power, performance and area (PPA)-driven spec‑to‑RTL generation, RTL analysis, and refinement; all from natural language prompts. Building on the industry’s first agentic workflow for front‑end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agen...

Cadence Tensilica IP Powers Analog Devices’ Next-Generation DSP Architecture

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced that its Tensilica IP Group and Analog Devices, Inc. (ADI) worked together to develop the latest generation of SHARC® automotive audio processors, further strengthening ADI’s industry-leading position in premium in-vehicle audio solutions. The joint effort brings Cadence’s highly optimized Tensilica DSP architecture into the next-generation ADSP product family from ADI, enabling richer audio experiences, enhanced voice in...
Back to Newsroom