SEOUL--(BUSINESS WIRE)--OPENEDGES Technology, Inc., the world’s leading supplier of AI computing IP solutions, announces semiconductor design IP (intellectual property: design asset) license agreement with a top-tier global semiconductor company.
The semiconductor IP (design assets) is the starting point of the semiconductor industry value chain, errors can cause critical defects in semiconductor chips during mass production, so semiconductor companies must be very precise and cautious. As a result, OPENEDGES design IP technology is well recognized by its worldwide customers in the semiconductor industry.
According to Mr. Sean Lee, CEO, OPENEDGES Technology, Inc., “Korea has an advanced environment with a well-established semiconductor industry ecosystem, but the AI Semiconductor IP field is still developing. We will keep dominating the market with our competitiveness of NPU and Memory Subsystem IP design technology in the edge computing market.”
The major design technology areas of OPENEDGES are NPU (Neural Processing Unit), which is an AI (Artificial Intelligence) accelerator, and the memory subsystem IP design that serves as a data pipeline for transferring and supporting the NPU’s main functions. The NPU is the next-generation semiconductor that acts like the human brain to process, for example, vision sensing data, which is unstructured information. OPENEDGES has enforced its global competitiveness by ensuring a platform that maximizes efficiency and simultaneously providing NPU and the subsystems to customers.
Currently, OPENEDGES has a number of fabless semiconductor customers in Korea and globally and is continuously striving to develop and expand in the global market.
About OPENEDGES Technology, Inc.
Founded in 2017, OPENEDGES is a semiconductor IP provider for AI computing and empowering the Internet of Smart Things. OPENEDGES is committed to democratizing artificial intelligence technology at the edge. OPENEDGES delivers IPs in two key technology areas of AI computing: highly efficient AI (Artificial Intelligence) acceleration and high-performance memory subsystem including NoC (Network on-Chip) bus interconnect IP, DDR controller and DDR PHY IP.
For more information, please visit: www.openedges.com