Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

Highlights:

• Certified Cadence flows are production-ready, and design IP is readily available for customers looking to create Intel 16 designs now
• Customers can confidently deliver a wide variety of HPC, consumer and USMAG applications based on the Cadence-certified flows

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its design IP supports this node from Intel Foundry Services (IFS). The companies also delivered the corresponding process design kits (PDKs) to accelerate the development of a wide variety of low-power consumer, high-performance computing (HPC) and secure U.S. Military, Aerospace and Government (USMAG) applications. Customers can begin using the production-ready Cadence^® design flows and design IP now to achieve design goals and speed time to market.

Intel 16 Digital Full-Flow

The complete Cadence RTL-to-GDS flow has been certified and optimized for use with Intel 16 technology, allowing customers to meet power, performance and area (PPA) targets. The flow includes the Innovus^™ Implementation System, Genus^™ Synthesis Solution, Quantus^™ Extraction Solution, Tempus^™ Timing Signoff Solution and Tempus ECO Option, Pegasus^™ Verification System and Pegasus DFM and Voltus^™ IC Power Integrity Solution. Some of the Cadence flow’s capabilities for Intel 16 process rules have been enhanced, including via insertion and antenna rule support, which ensure high-quality designs.

Intel 16 Custom/Analog Flow

Cadence Virtuoso^® Studio, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso ADE Suite, and the integrated Spectre^® X Simulator, have all been certified for Intel 16 technology. These tools have all been enhanced for better management of corner simulations, statistical analyses, design centering and circuit optimization.

The Virtuoso design platform provides a tight integration with the Innovus Implementation System, enhancing the implementation methodology of mixed-signal designs using a common database. In addition, the Virtuoso Layout Suite has been refreshed for efficient layout implementation on Intel 16, which leverages better performance and scalability throughout the layout environment; a non-uniform grid-based device place-and-route methodology with interactive, assisted features for placement, routing, fill and dummy insertion; width-based spacing pattern (WSP) support; integrated parasitic extraction and EM-IR checks; and integrated signoff-quality physical verification capabilities using Virtuoso InDesign DRC.

Intel 16 Design IP

Cadence Design IP has been ported and silicon-tested for Intel 16 technology and including the enterprise-class PCI Express^® (PCIe^®) 5.0 and 25G-KR Ethernet multi-protocol PHY; multi-protocol PHY for consumer applications supporting standards such as PCIe 3.0 and USB 3.2; multi-standard PHY for LPDDR5/4/4X to enable a diverse set of memory applications; MIPI^® D-PHY℠ v1.2, enabling a broad range of MIPI consumer applications such as cameras and displays; and MIPI SoundWire^® I/O for audio applications.

“Our mutual customers create designs for a wide range of vertical markets, and in particular, the USMAG market has really come to rely on us as their trusted foundry partner due to their unique security requirements,” said Rahul Goyal, vice president & general manager for Intel’s Product & Design Ecosystem Enablement group. “Through our ongoing collaboration with Cadence, we’re empowering customers in all markets to unlock the power-saving benefits that come with our Intel 16 technology and the advanced Cadence flows and IP.”

“The Cadence R&D team collaborated with IFS to certify its flows and design IP for the Intel 16 process technology, ensuring customers have a fast path to adopt our technologies to deliver innovative consumer and USMAG applications in a timely manner,” said Nimish Modi, senior vice president and general manager, Strategy and New Ventures at Cadence. “With chip design innovation continuing to evolve at such a rapid pace, our customers can design with confidence, knowing that we’ve optimized our tools and IP so they can meet the most challenging design requirements.”

Cadence advanced-node EDA solutions and IP support the company’s Intelligent System Design^™ strategy, enabling customers to achieve SoC design excellence. For more information on Cadence advanced-node solutions, visit www.cadence.com/go/advndifspr.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. MIPI, D-PHY, and SoundWire are registered trademarks or service marks owned by MIPI Alliance. PCI Express and PCIe are registered trademarks or trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

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