SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Arm is leveraging Cadence® Liberate™ MX Trio Characterization to enhance the quality of its embedded memory instances and compilers and speed time to market. With Liberate MX Trio Characterization, Arm achieved its accuracy and capacity requirements and reduced memory liberty variation format (LVF) characterization validation runtime by 7X when compared with brute-force Monte Carlo simulation.
Liberate MX Trio Characterization, a library characterization solution that is suited for large, advanced-node memory designs, enabled the Arm engineering team to efficiently and accurately perform characterization validation of its embedded memory instances and compilers. Unlike traditional solutions that require tradeoffs between runtime and accuracy, Liberate MX Trio Characterization provided Arm with automated and simulation-based dynamic partitioning to reduce runtime, increase capacity and maintain SPICE-level accuracy. In addition, the Liberate MX Trio Characterization’s probing capabilities helped Arm identify the most critical timing arcs and reduce the manual effort associated with characterization path selection. Simulations on the full RC netlist covering a complete vector set let Arm identify accurate worst-case paths and maintain SPICE-level accuracy. Moving from Arm’s previous brute-force Monte Carlo simulation methodology to the Liberate MX Trio Characterization variation LVF analysis methodology saved Arm weeks of validation time through the solution’s automated and less error-prone methodology.
“Arm has been leveraging the Liberate Trio Characterization Suite for standard cell characterization, so it was an easy choice for us to broaden our deployment with Liberate MX Trio Characterization to address our evolving LVF memory characterization needs,” said Philippe Moyer, VP Design Enablement, Physical Design Group, Arm. “By incorporating Liberate MX Trio Characterization into our methodology, we are improving accuracy, capacity and meeting time-to-market goals with the delivery of our embedded memory instances and compilers.”
“Memory characterization can have a significant impact on signoff accuracy, and Arm was looking for a reliable solution for its embedded memory IP that would help them achieve their accuracy requirements while speeding time to market,” said Sharad Mehrotra, VP of R&D, in the Digital & Signoff Group at Cadence. “Arm joined a community of successful, production-proven Liberate MX Trio Characterization customers, trusting the solution for its memory characterization needs and expanding upon its use of the broader Liberate product portfolio for standard cell power and performance characterization.”
The Liberate MX Trio Characterization is part of the broader digital full flow, which supports the company’s Intelligent System Design™ strategy and enables SoC design excellence. For more information on Liberate MX Trio Characterization, please visit www.cadence.com/go/liberatemxcs.
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