OneSpin Solutions to Participate at the 57th Design Automation Conference Highlighting Certified IC Integrity Verification Solutions in the Technical Program

Security, Automotive Safety, RISC-V, Nuclear Energy Topics Tackled During Sessions

MUNICH--()--OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits will have a visible presence at the upcoming Design Automation Conference, being held virtually July 20 – 24, 2020. OneSpin’s experts will be participating in two Research Track sessions, the RISC-V Theater and several technical poster sessions in the Designer Track and IP Track.

Along with participating in DAC’s technical program, OneSpin will highlight its full complement of certified IC integrity verification solutions at the virtual DAC exhibition held Monday, Tuesday, Wednesday, July 20 – 22, from 10:30 a.m. until 1:30 p.m. PDT.

For more information on OneSpin at DAC 2020 visit: https://www.onespin.com/dac

FMEDA for Automotive ISO 26262
Designer Embedded and IP Track Poster session (126.34)
Tuesday, July 21, 7:30 a.m. PDT

Quantitative FMEDA for automotive applications and compliance with ISO 26262 can be challenging. Fault injection can be used for deriving hardware safety metrics. However, for complex chips or semiconductor IPs with a variety of safety mechanisms, using fault simulation is laborious and time-consuming. What are the right stimuli to use? How can I speed up fault simulation? How can I detect early in the flow if the safety architecture will not get me to the target SPFM and LFM metrics, whether my goal is an ASIL-B, ASIL-C, or ASIL-D system? The good news is that there are alternative ways to approach the problem that can reduce or even eliminate the need for fault simulation.

FPGAs for Nuclear I&C
Designer Embedded and IP Track Poster session (126.83)
Tuesday, July 21, 7:30 a.m. PDT

The IEC SC 45A standard series regulates electronic instrumentation and control equipment in nuclear energy applications. In particular, IEC 62566 focuses on FPGA development activities, including verification of the post-synthesis and post-place-and-route netlists. How can you reduce the need for slow gate-level simulations? How can you be sure that the implementation tools have not introduced errors? Is that possible when using more advanced implementation flows? Luckily, there are formal verification tools that are dedicated to FPGA flows. With a few days of effort, it is possible to exhaustive verify large netlists. Crucially, these tools are independent of the implementation tools, an essential requirement from safety standards.

IP Track Session: Automated Trust and Assurance of IPs
Trends in Meeting IP Challenges for a New Decade session (19.2)
Thursday, July 23 1:30 p.m. - 3:00 p.m. PDT

Developers of safety- and security-critical SoCs can no longer afford to ignore the risks of security vulnerabilities when integrating third-party IPs. Re-verification of an IP is not feasible, and the cost is prohibitive, even more so when the implementation-level expertise is not in-house. Verification and code reviews are likely to miss stealthy Trojans or vulnerabilities that surface in deep corner-case, misuse scenarios that are far from the IP intended usage. Some solutions are emerging to address these challenges. The Aerospace Corporation and OneSpin will share results of the application of an automated IP trust and assurance flow on over 90 RTL designs

RISC-V Security and Assurance
Designer Embedded and IP Track Poster session (126.53)
Tuesday, July 21, 7:30 a.m. PDT

RISC-V has reinvigorated the open-source hardware community. Many individuals, companies, and organizations, including the OpenHW Group, are continuously releasing new and updated implementations of the RISC-V ISA. However, thorough functional verification of processors is very costly. Established IP providers using proprietary architectures have decades of experience and enormous resources dedicated to functional verification. And yet, security issues are routinely missed. RISC-V makes it possible and affordable to take the assurance and security verification of processor cores to the next level, matching or even exceeding the quality of established IP providers. Edaptive Computing and OneSpin will share results of the application of a RISC-V formal verification solution to two cores (RocketCore and OpenHW CV32E40P).

RISC-V Theater: Integrity Verification Solution
Tuesday, July 21, 11:30 a.m. - 11:50 a.m. PDT

Leaders in the RISC-V ecosystem have a dedicated DAC 2020 event: the RISC-V Theater. OneSpin will present its RISC-V Integrity Verification Solution and share the results of formal verification of RISC-V cores and SoCs.

Processor Side-channels
Trust...but Securely Verify research session (87.3)
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-Of-Order Processors
Friday, July 24, 2:00 p.m. – 3:00 p.m. PDT

Hardware security weaknesses and vulnerabilities are leveraged in ever more exploits. Since the discovery of the Meltdown and Spectre in early 2018, micro-architectural side-channels and transient execution attacks have become a gold mine for security researches and, possibly, hackers. While there are no systematic processes and tools that address this risk comprehensively, research efforts are showing promising results. The Unique Program Execution Checking (UPEC) method introduced in this paper is based on formal methods. The paper demonstrates that it is possible to analyze a processor RTL implementation and systematically detect vulnerabilities that can derive from the processor microarchitecture and even from minor implementation choices. In the DAC 2020 paper authored by staff at the University of Kaiserslautern, Germany, Stanford University, California, and OneSpin’s CEO Raik Brinkmann, the authors extend their previous work on UPEC to more complex, out-of-order processors.

About OneSpin Solutions

OneSpin Solutions is a leading provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits. These solutions are based on OneSpin's widely used formal verification technology and assure the integrity of SoCs, ASICs and FPGAs. Headquartered in Munich, Germany, OneSpin partners with leaders worldwide in automotive and industrial applications; defense; avionics; artificial intelligence and machine learning; consumer electronics; and communications. Its advanced solutions are well-suited for developing heterogeneous computing platforms, using programmable logic, and designing and integrating processor cores, such as RISC-V. OneSpin's customer-oriented commitment is fundamental to its growth and success. OneSpin: Assuring IC Integrity. Visit www.OneSpin.com to learn more.

OneSpin, OneSpin Solutions and the OneSpin logo are trademarks of OneSpin Solutions GmbH. All other trademarks are the property of their respective owners.

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Contacts

Media contact US:
Michelle Clancy, Cayenne Communication
Tel.: 503.702.4732, Michelle.clancy@cayennecom.com

Media contact Europe:
Annette Bley, Annette Bley PR
Tel: +44 (0)7973 801132, annette@annettebleypr.com

Release Summary

OneSpin Solutions to Participate at the 57th DAC Highlighting Certified IC Integrity Verification Solutions in the Technical Program

Contacts

Media contact US:
Michelle Clancy, Cayenne Communication
Tel.: 503.702.4732, Michelle.clancy@cayennecom.com

Media contact Europe:
Annette Bley, Annette Bley PR
Tel: +44 (0)7973 801132, annette@annettebleypr.com