Aldec and Tamba Networks Release Ultra Low Latency Ethernet Solution for UltraScale+ FPGA at The Trading Show 2018

CHICAGO--()--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has utilized Aldec’s HES-XCVU9P-QDR UltraScale+ board with Tamba Networks’ 10G Ethernet MAC IP Core to deliver a proven Ultra-Low Latency (ULL) Ethernet solution that provides ~56ns roundtrip Ethernet latency using QSFP28 channels.

“High Frequency Trading (HFT) firms need the fastest and latest technology in their arsenal in order to compete in the financial markets. Since FPGAs consist of millions of logic gates that can be configured to process the network data in a highly parallel architecture and deterministic behavior, FPGAs can reliably provide nanosecond Ethernet latency,” said Louie De Luna, Aldec’s Director of Marketing. “Our solution with Tamba Networks is an FPGA implementation of a highly optimized FIFO + MAC + PCS running on the latest Xilinx® UltraScale+™ architecture.”

“In recent years, latency has become a key differentiator for financial markets firms attempting to reduce tick to trade latency, and there has been a gradual trend from software-based trading to hardware accelerated trading. In the five years, since launch of the Ethernet products, Tamba has become the dominant low latency supplier in financial markets, which would not be possible without high quality hardware platforms from companies such as Aldec,” said Soren Pederson, President of Tamba Networks.

Aldec’s HES-XCVU9P-QDR board contains a Xilinx® Virtex™ UltraScale+ XCVU9P FPGA with 2x 100 Gb/s QSFP28 cages. The reconfigurable FPGA, combined with QDR-II+ or DDR4 memory modules, provide high throughput for algorithm acceleration and data processing using the PCIe interface protocol. The PCIe x16 half-length low-profile board is 1U compatible and easily fits into enterprise rack systems for maximum performance density.

Tamba’s 10G Ethernet MAC IP features include IEEE Compliance, Configurable IPG w/ DIC, Configurable preamble size, Preamble contents as sideband signal on SOP, Pause Port & PFC, PTP/1588, Pad insertion, Jumbo Frames, Statistics Aggregation, Configurable System/Core/PMA Bus Width, Latency, power and gate count lowest in the market.

Aldec’s HES-XCVU9P-QDR is now ready for shipment - Download Tech Specs here. Aldec’s HFT boards can also be bundled with Aldec’s Riviera-PRO Advanced RTL Simulator and ALINT-PRO Design Rule Checker.

The solution will be showcased at The Trading Show 2018, to be held on May 9-10, 2018, in Chicago, IL - Aldec booth #112 and Tamba Networks booth #120.

See Aldec’s Presentation at The Trading Show 2018, May 9, 2018, 11:10 a.m. – Best-Practices in Designing High-Speed FPGA Systems.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, SoC and ASIC Emulation/Prototyping, Design Rule Checking, CDC/RDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solution, High-Performance Computing and Military/Aerospace solutions. www.aldec.com

About Tamba Networks

Based in Silicon Valley the portfolio includes IP solutions consisting of a complete family of silicon-proven soft Ethernet and Interlaken cores. With a robust IP development methodology, extensive investment in quality, IP prototyping, and comprehensive technical support, Tamba enables designers to accelerate time-to-market and reduce integration risk, with performance that is absolutely unmatched in the marketplace. For more information, please visit: http://www.tambanetworks.com

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Contacts

Aldec, Inc.
Richard Warrilow, +44 (0)1522 789000
richardw@aldec.com

Contacts

Aldec, Inc.
Richard Warrilow, +44 (0)1522 789000
richardw@aldec.com