BERKELEY, Calif.--(BUSINESS WIRE)--The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced that the Association for Computing Machinery (ACM) named David A. Patterson––emeritus professor at UC Berkeley, distinguished engineer at Google, and Vice Chair of the Board for the RISC-V Foundation––a recipient of the 2017 ACM A.M. Turing Award. This award recognizes individuals for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with an enduring impact on the microprocessor industry. Patterson accepted this honor with longtime colleague, John L. Hennessy, former President of Stanford University.
As Professor of Computer Science at the University of California, Berkeley, Patterson led the Berkeley RISC project and now is an active member of the RISC-V Foundation, which offers a free and open ISA with the aim of enabling a new era of processor innovation through open standard collaboration.
“I’m honored to receive the ACM A.M. Turing Award, in union with my good friend and co-author John Hennessy,” said David Patterson. “The RISC-V approach and ISA has ushered in a new era of processor innovation through a truly free and open standard collaboration that lets everyone participate in this new Golden Age of computer architecture. I’m proud of the work that has been done and look forward to what we are able to achieve in the future.”
Since its inception in 2015, the RISC-V Foundation has quickly expanded its ecosystem to more than 100 organizations, individuals, academics and universities from around the world, all working together to enable a wide range of open-source and proprietary RISC-V hardware and software solutions. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
“For the past 30 years, Dave has been a catalyst in the advancement of RISC architectures and the expansion of the RISC-V Foundation and the ecosystem of RISC-V currently embraced today. Congrats to my colleague and friend, Dave, on this tremendous honor,” said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation.
The ACM A.M. Turing Award, often referred to as the “Nobel Prize of Computing,” carries a $1 million prize, with financial support provided by Google, Inc. It is named for Alan M. Turing, the British mathematician who articulated the mathematical foundation and limits of computing.
“ACM initiated the Turing Award in 1966 to recognize contributions of lasting and major technical importance to the computing field,” said ACM President Vicki L. Hanson. “The work of Hennessy and Patterson certainly exemplifies this standard. Their contributions to energy-efficient RISC-based processors have helped make possible the mobile and IoT revolutions. At the same time, their seminal textbook has advanced the pace of innovation across the industry over the past 25 years by influencing generations of engineers and computer designers.”
Patterson and Hennessy will formally receive the 2017 ACM A.M. Turing Award at the ACM’s annual awards banquet on June 23, 2018 in San Francisco.
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About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.