SAN JOSE, Calif.--(BUSINESS WIRE)--Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries today announced support for the SpyGlass platform working with the Xilinx® Vivado® Design Suite including support for IEEE 1735 encrypted models and hard macros. With this support, customers will be able to perform comprehensive CDC analysis on RTL designs with embedded Xilinx encrypted IP and hard macros.
As FPGA capacity grows, an increasing number of chip designers are targeting System on Chip (SoC) designs on FPGA platforms. To address this growing complexity, FPGA vendors like Xilinx are providing more and more IP blocks for standard functions to maximize design reuse, lower power, and improve efficiency. A significant share of these IP is delivered to customers either encrypted or as hardened macros by Xilinx. Traditionally, 3rd party EDA tools for RTL analysis and verification have treated these as black boxes for lack of visibility into the internals. This approach can be error-prone, especially for CDC verification where it is essential to trace all paths leading into and out of these IP. Atrenta has collaborated with Xilinx to add support for these blocks seamlessly in SpyGlass using IEEE 1735 encryption and also leveraging industry standard models for hard macros.
“Xilinx provides the most comprehensive solutions to our customers by combining the Vivado Design Suite with industry leading tools from our ecosystem of Alliance member companies”, said Tom Feist, senior design methodology marketing director at Xilinx. “The collaboration with Atrenta provides Vivado users the benefit of a complete and seamless clock domain verification flow with Atrenta’s SpyGlass CDC.”
The new integration of SpyGlass and Vivado is available with the Xilinx Tcl Store and enables easy setup and launch of SpyGlass for the end user. This flow leverages both the Xilinx UltraFast™ Design Methodology and the SpyGlass GuideWare methodology to perform accurate and comprehensive CDC analysis across the entire design, including non-RTL hard macros and IEEE 1735 encrypted RTL blocks.
“As the gold standard for RTL Signoff, we are excited to extend our solutions to the fast growing FPGA design community,” said Piyush Sancheti, vice president of marketing at Atrenta. “Verification of clock domain crossings and metastability issues is mission critical for SoC designs with multiple asynchronous clock domains. This collaboration with Xilinx will benefit our mutual customers in utilizing the full potential of the industry leading CDC solution.”
Atrenta and Xilinx will showcase their collaboration at the Atrenta booth (#1732) at the 52nd Design Automation Conference (DAC) in San Francisco, CA. For details and signup, please visit www.atrenta.com/DAC2015. This enhanced SpyGlass Flow for Xilinx FPGAs is available in the SpyGlass 5.5 release scheduled for late June. The respective tools can be purchased from Xilinx and Atrenta.
About Atrenta Inc.
Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred eighty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. With the addition of GenSys® and BugScope®, RTL modification and verification efficiency are also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
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This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.