SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced new design flows based on the Cadence® Integrity™ 3D-IC platform to support the TSMC 3Dblox™ standard for 3D front-end design partitioning in complex systems. Through this latest collaboration, the Cadence flows are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications.
The Cadence Integrity 3D-IC platform combines system planning, packaging, and system-level analysis and is a complete solution certified for use with the TSMC 3DFabric and the 3Dblox 1.5 specification. The flows based on this platform incorporate several new features like 3D routability-driven bump assignment and hierarchical bump resource planning. 3Dblox, which is inherently supported by the Integrity 3D-IC platform, provides a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus™ IC Power Integrity Solution and Celsius™ Thermal Solver system analysis tools; extraction and static timing analysis via the Cadence Quantus™ Extraction Solution and Tempus™ Timing Signoff Solution; and system-level layout versus schematic (LVS) checks via the Cadence Pegasus™ Verification System.
“3D-IC technology is key to meeting the performance, physical size, and power consumption requirements to enable next-generation HPC and mobile applications,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By continuing our collaboration with Cadence, we’re enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows that support our 3Dblox standard, so they can significantly improve 3D-IC design productivity and speed time to market.”
“The Cadence flows based on the Integrity 3D-IC platform incorporate everything a customer needs to quickly design a leading-edge 3D-IC using TSMC’s latest 3DFabric technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Through our extensive work with TSMC, we’re jointly resolving the 3D-IC design challenges our customers regularly face, putting them on an accelerated path to bring innovative designs to life.”
The Cadence Integrity 3D-IC platform, including Allegro X packaging technologies, is part of the company’s broader 3D-IC offering and aligns with the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. The Cadence reference flows and tutorials are available on TSMC Online now, and more information on the Integrity 3D-IC platform can be found at www.cadence.com/go/integrity3dblox.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
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