DUBLIN--(BUSINESS WIRE)--The "Hybrid Bonding Patent Landscape Analysis" report has been added to ResearchAndMarkets.com's offering.
The pace of Moore's law is slowing, if it has not already stopped, as mentioned by Forbes and Nvidia. It's reaching its limits because developing smaller technology nodes is doable technically, but is no longer cost-efficient. The digital electronics market requires a higher density semiconductor memory chip to cater to recently released central processing unit (CPU) components. To answer the growing demand and overcome Moore's law's limits, multiple die stacking has been suggested as a solution. Advanced packaging technology development, specifically 2.5D technology, was first used in high-performance applications. Today, scaling the Z-axis is becoming more and more important in what is called 3D stacking.
Generally, 2.5D-3D stacking was achieved thanks to Through Silicon Via (TSV) technology. However, TSVs are large and using them limits efforts to reach very dense architectures. Furthermore, filling TSVs with metals is complex and requires significant know-how. To overcome these limitations, players have started to look at other solutions. A first step toward a new way of 3D stacking is ZiBond, developed by Ziptronix, a company founded in 2000 as a spin-out of Research Triangle Institute. ZiBond is an enhanced version of direct oxide bonding that involves wafer-to-wafer processing at low temperatures, from 150-300C, to initiate high bond strengths, rivaling silicon. The next step was to combine the dielectric bond with embedded metal to simultaneously bond wafers or bond dies to wafers and form the interconnects. ZiBond is the dielectric bond that forms the basis for direct bonding interconnect (DBI) technology developed in 2005. Tessera, now called Xperi, acquired Ziptronix in 2015 and ZiBond and DBI were integrated in the Invensas subsidiary's portfolio. This hybrid bonding technology is quickly becoming recognized as the preferred permanent bonding path to form high-density interconnects in heterogeneous integration applications, from 2D enhanced, to 3D stacking with or without TSVs, as well as MEMS.
After entering the CMOS Image Sensor (CIS) market in 2016, hybrid bonding technology has started to be investigated by other industries, such as memory. However, the hybrid bonding market's growth follows Xperi's developments. The company has adopted an aggressive strategy to assert its patents. Yet in parallel with the market and Xperi's growth, some other players, like YMTC, Sony, Samsung and TSMC, have developed their own patent portfolios and strategies and are on the edge of releasing their first products using hybrid bonding processes. Understanding the IP landscape is becoming key to evaluate the risks and opportunities that go with the development and use of hybrid bonding technology.
Main IP player ranking
IP player current developments
This report reveals all players developing IP related to hybrid bonding per type of targeted applications and shows companies' current developments. Learn how they integrate hybrid bonding in their manufacturing process flow. Detect your future competitors or partners and evaluate their know-how, IP strength, IP weaknesses and the risk of infringing their patents.
Main IP players' portfolio analysis
Report's Key Features
- PDF with > 80 slides
- Excel file > 1,000 patents
- IP trends, including time-evolution of published patents, countries of patent filings, etc.
- Ranking of main patent assignees
- Key players' IP position and relative strength of their patent portfolios
- Patent segmentation per application:
- CMOS image sensor (CIS)
- Memory
- MEMS
- LED
- Key patent identification and details
- IP profile of key players: Xperi, TSMC, YMTC
- Excel database containing all patents analyzed in the report, including technology and application segmentations
Key Topics Covered:
1. INTRODUCTION
- Context and market
- Manufacturing process
2. SCOPE AND METHODOLOGY
- Scope of the report
- Key feature of the report
- Main assignees citing in the report
- Objectives of the report
- Methodology for patent search and selection
- Terminologies for patent analysis
- Definition for key patents
3. IP LANDSCAPE OVERVIEW
- Time evolution of patent publications
- Main IP players
- Legal status of patents
- Geographic coverage of IP portfolios
- Time evolution of patent publications per assignee
- IP position of main IP players
- IP leadership
- IP blocking potential
- Strength index
4. CORPUS SEGMENTATION
- Position on the supply chain
- Hybrid bonding process
- Devices using hybrid bonding technology
- Applications:
- CMOS image sensor (CIS)
- Memory
- MEMS
- LED
5. KEY PATENTS
6. LITIGATION
7. IP PROFILE OF KEY PLAYERS
- Main IP players
- TSMC
- Xperi
- IP Newcomers
- YMTC
8. CONCLUSION
Companies Mentioned
- Xperi
- TSMC
- YMTC Samsung Electronics
- Sony
- Cea
- Canon
- Renesas Electronics
- Raytheon, Apple
- Stmicroelectronics
- SMIC
- Intel
- Seoul National University Industry Foundation
- Shanghai Ic R&D Center
- XMC
- Omnivision Technologies
- IMEC
- Monolithic 3D
- Nanya Technology
- Katholieke Universiteit Leuven
- Globalfoundries
- American Business Grid Ic Technology
- ON Semiconductor
- Qualcomm
- NCap
- Lexvu Opto Microelectronics Technology
- Intellectual Ventures
- Magnachip Semiconductor
- IBM
- Atri
- Institute Of Microelectronics Chinese Academy Of Sciences
For more information about this report visit https://www.researchandmarkets.com/r/llsv2t
