HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, is celebrating its 35th Anniversary at the 2019 Design Automation Conference (DAC), June 2-6, Las Vegas, NV, and has prepared technical presentations aligned with many of the industry’s hottest topics.
“This year’s DAC is a very special one for us as it’s our 35th anniversary and is in Las Vegas, our home city,” says Zibi Zalewski, General Manager of Aldec’s Hardware Division. “During the conference our engineering team will be presenting the latest solutions for a complete verification flow, including multi-language, mixed-signal simulation and hardware emulation and multi-FPGA prototyping. Our technology experts will also be showcasing our latest embedded solutions for 4k video processing and DNN-based object classification using the latest FPGA platforms.”
The following presentations will be offered continuously throughout the three main days of DAC – June 3, 4 and 5 - on Aldec’s booth (#623):
- 4k Video Processing Embedded System Design by the Example of Optical Flow
- AI on The Edge – DNN-based Object Classification on TySOM EDK
- Hybrid Co-Emulation with ARM Hardware Model
- Partitioning Design for Multi-FPGA Prototyping
- Aldec and Silvaco Mixed-Signal Simulation
- SoC Simulation Environment for Mixed-Signal Designs
- Register Generator for Design Register and Memory Management
- Advanced UVM tools in Riviera-PRO™
Each presentation will last about 30 minutes and interested parties are advised to pre-register to select their preferred subject matter and to secure their preferred date and time slot; where presentation start times commence at 10:00 and end at 17:30.
Also, all who attend a presentation will automatically be entered into a prize draw, as Aldec is giving away an Apple product on each of the show’s main three days. The prizes and their corresponding draw days are: an Apple iPad, on June 3; an Apple Smart Watch, on June 4; and an Apple MacBook Air, on June 5. Each day’s winner will be drawn at 17:00.
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.