SAN FRANCISCO--(BUSINESS WIRE)--DESIGN AUTOMATION CONFERENCE--A new electronic design automation (EDA) company and a groundbreaking new product were launched at DAC 2012 today. Ausdia delivers a comprehensive timing constraints development, verification and management solution that complements all implementation and timing signoff flows. Ausdia’s Timevision, an innovative timing constraint development solution, integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC/TCL constraints and is a verification platform for existing timing constraints. The company’s technology represents a new way for system-on-chip (SoC) and integrated circuit (IC) developers to make massive productivity gains across the design flow.
Silicon designs are becoming progressively more complicated, and harder to design and verify. SoCs drive increasing complexity – in terms of raw design size, use of IP blocks, technology node, number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes. Ausdia’s founders realized that a comprehensive product for timing constraints generation and validation would be needed and that it would have to correlate with static timing analysis engines to ensure correctness. Using multicore software design, patent-pending analysis algorithms, and innovative formal verification technology, Timevision was built specifically to handle very large, complex SoC designs (especially above 50M gates).
Timevision delivers runtimes that are 3 to 10x faster than static timing analysis (STA) tools – a standard benchmark when evaluating constraint verification technologies. Ausdia technology also overcomes the problem of huge amounts of “static analysis noise,” which can make diagnosis a time-consuming problem. Timevision delivers concise summary outputs that can progressively be expanded, rather than being overwhelming from the start. The company also has developed a solution to help designers find their most complex “timing relief” optimizations towards the tail end of the chip design process using high-performance formal analysis techniques.
“In our experience, timing constraints are the most common cause for timing closure to fail or to take too long – and it’s usually realized far too late in the design process, causing significant impact to tapeout schedules,” said Sam Appleton, president and CEO of Ausdia. “If the timing constraints for a complex design are bad, it either won’t close timing or will come back from the foundry not working. Timing constraint development requires an integrated, high-performance solution like Timevision, especially for any design team working with large, complex SoCs or IPs.”
Early users of Ausdia technology agree that productivity improvements and quality of results have been impressive:
Ausdia, a privately-held company with no external investors, was formed in late 2006 and began product development in 2008, with the first timing constraints product reaching the market in 2010. All members of the founding team have taped out multiple chips, and are acutely aware of the pain that chip designers go through at the pressure point between design and release-to-foundry.
Founders include:
- Sam Appleton, PhD (University of Adelaide, Australia), president and CEO. Prior to founding Ausdia, Sam held a variety of technical leadership roles at Azul Systems, ReShape, Cosine Communications and Silicon Graphics.
- Atul Bhagat, MSEE (Stanford), CTO. Prior to co-founding Ausdia, Atul was the timing analysis, timing closure and chip integration technical lead at Azul Systems, Reshape, nVIDIA, and Sun Microsystems.
- Timothy Moore, BSEE (NC State), founding software architect, has been involved with developing Ausdia’s core technology since 2008. A 20+-year veteran of the EDA industry, Tim was a member of the original founding team of Synopsys and later a principal engineer at Synopsys as well as an EDA industry software consultant.
More about Timevision
Timevision represents a new way for STA engineers to massively increase their productivity -- by operating as constraint synthesizers, rather than line-by-line writers and debuggers. Timevision also integrates a variety of formal, structural and simulation-based technologies to aid STA engineers in the quick and confident development of constraints from high-level data.
Timevision brings this same capability to RTL designers, who are often under more pressure to be involved with timing closure (but lack the time available to dive into gate-level issues), and to implementation engineers trying to make sense of constraints and how best to implement their designs (but lack the detailed knowledge of the design).
Timevision is based on a standard TCL shell, so the integration and user interface is easily understood by anyone who has used STA or synthesis tools. Runtimes measure in minutes, so constraints can be checked rapidly, in real time, without waiting for multi-hour runs. The platform also handles every variant of multi-language designs – Verilog, gate, SystemVerilog and all VHDL variants – allowing all designs that will read into a synthesis tool to be read into Timevision, with almost no change to the scripting flow.
“I think the thing I’m most proud of over the last two years is that we’ve never let up on improving the product, to the point that things that used to take us several hours now take just minutes,” said Atul Bhagat, CTO. “Chip designers really put in some serious hours, under intense pressure, and I am glad that we are able to continually introduce productivity gains that help them in their efforts.”
Pricing and Availability
Timevision is available now. U.S. pricing for a yearly base package starts at $125k per license.
Ausdia will be exhibiting Timevision in Booth #1505 at DAC 2012 in San Francisco from June 4th-7th.
About Ausdia
Ausdia delivers standout timing constraint development, verification, and management solutions that complement all implementation and timing signoff flows. The company’s groundbreaking methodology and products give system-on-chip (SoC) and integrated circuit (IC) developers a new way to work, enabling massive productivity gains throughout the design flow. Founded in 2006, the privately-held company is headquartered in Sunnyvale, California.