Compute Express Link™ (CXL™) Consortium Takes the Stage at Flash Memory Summit (FMS) 2023 in Santa Clara
Compute Express Link™ (CXL™) Consortium Takes the Stage at Flash Memory Summit (FMS) 2023 in Santa Clara
Consortium representatives will highlight CXL technology in various sessions during the show.
BEAVERTON, Ore.--(BUSINESS WIRE)--The Compute Express Link™ (CXL™) Consortium, an industry standards body developing and promoting an open coherent interconnect, will provide an update on CXL technology, highlight updates to the Consortium’s Compliance and Interoperability Program, and showcase CXL technology demo videos in the SNIA Open Standards Pavilion (booth #725) at FMS 2023.
FMS is taking place August 7 – 10 at the Santa Clara Convention Center in Santa Clara, CA and attendees are encouraged to attend the CXL Consortium’s pre-conference seminar Monday, August 7, from 8:30 am – 12:00 pm PT in Room 210. CXL Consortium Technical Task Force Co-Chair, Mahesh Wagh, will provide a deep dive into the CXL 1.1, 2.0 and 3.0 specifications and explore memory pooling and sharing enhancements. Finally, CXL Consortium representatives will discuss use cases for CXL technology and the expanded capabilities the technology allows.
Contact press@computeexpresslink.org to schedule a meeting with CXL Consortium representatives at the event.
What: |
CXL Consortium at FMS 2023 — register here |
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Who: |
CXL Consortium will have a kiosk in the SNIA Open Standards Pavilion booth #725 |
Pre-conference seminar: Introduction to CXL |
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Presentation: Compute Express Link (CXL) 3.0: Enhancements to memory pooling and sharing |
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Panel presentation: Compute Express Link (CXL) Device Ecosystem and Usage Models |
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Where: |
Santa Clara Convention Center |
Santa Clara, CA |
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When: |
Monday, August 7 – Pre-conference sessions at 8:30 am PT |
Tuesday, August 8 – Thursday, August 10 |
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Exhibit show floor hours: |
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About the CXL™ Consortium
The CXL Consortium is an industry standards body dedicated to advancing Compute Express Link™ (CXL™) technology. CXL is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. For more information or to join, visit www.computeexpresslink.org.
Contacts
Elza Wong
Nereus
+1 503.680.9170
press@computeexpresslink.org