SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology. This certification ensures Cadence and Samsung Foundry mutual customers of a highly automated circuit design, layout, signoff and verification flow with full extreme ultraviolet lithography (EUV) support. This certification complements the earlier announced certification of the Cadence® full-flow digital and signoff tools on Samsung 7LPP process technology.
For more information on the new Cadence custom/AMS flow, visit www.cadence.com/go/samsung7lppams.
The Cadence custom and AMS flow includes the Virtuoso® Analog Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite with its Advanced-Node Platform, Virtuoso Space-Based Router, Spectre® Circuit Simulator, Voltus™-Fi Custom Power Integrity Solution, Quantus™ Extraction Solution, Physical Verification System, Litho Physical Analyzer, Cadence CMP Predictor and LDE Electrical Analyzer. These tools can be used throughout the complete custom AMS flow, including:
- Front-end design: Corner, statistical, and reliability simulation; circuit and device checks; layout-dependent effect (LDE) analysis, and simulation and verification management.
- Custom layout design: An advanced, electro-migration and parasitic-aware environment that includes device and module generation, automated placement and routing, layout editing, and dynamic DRC checking with Virtuoso Integrated PVS DRC, interactive PVS metal fill, in-design DFM flows for LDE, process hotspot repair (PHR), pattern analysis and optimization, and chemical mechanical polishing (CMP) check, as well as support for correct-by-design multiple patterning flow.
- Post-layout parasitic simulation and IR drop (IREM) analysis and integrated signoff: Including parasitic extraction, design rule checks, layout versus schematic checks, dummy metal fill and programmable electrical rule checks (PERC).
- AMS design: Digital standard cell placement, pin optimization and automated space-based routing.
“In close collaboration with Samsung, we have delivered a certified, integrated flow for custom and AMS design at 7LPP technology based on our industry-leading Virtuoso and Spectre platforms,” said Wilbur Luo, Cadence vice president, product management, analog/custom marketing. “Samsung customers can now take advantage of the most advanced features for circuit design, performance and reliability verification, and automated layout, block and chip integration for custom and digitally controlled analog designs.”
“By working closely with Cadence, we can provide our customers the most advanced FinFET performance for their custom and AMS chip designs,” said Ryan Lee, vice president of Foundry Marketing at Samsung Electronics. “Cadence helps us offer our customers the best power, performance and area for their leading-edge designs.”
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
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