--(BUSINESS WIRE)--RISC-V Foundation:
|Linley Processor Conference 2017, Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, Calif., 95054|
|Wednesday, Oct. 4 to Thursday, Oct. 5, 2017|
|The RISC-V Foundation, together with members including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive, will exhibit new RISC-V implementations at the Linley Processor Conference 2017. Named the 2016 “Best New Technology” for the Linley Group Winners of Annual Analysts’ Choice Awards, the RISC-V community of software and hardware companies continues to grow, making the open and free RISC-V ISA the industry’s de facto standard for future design innovation. Additionally, RISC-V Foundation members, UltraSoC and SiFive, will present at this year’s show, speaking sessions include:|
Introducing the New RISC-V U54 Coreplex
- When: Wednesday, Oct. 4, 2017 at 1:50 – 3:30 p.m. PT
- Who: Jack Kang at SiFive
SoCs Need a System-Level Approach: The Case for Embedded Analytics
- When: Tuesday, Oct. 5, 2017 at 8:45 – 10:30 a.m. PT
- Who: Gajinder Panesar at UltraSoC
To schedule a meeting with RISC-V or a member organization please email: email@example.com. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 70 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.