Ziptronix and Customer Pursue Lower-Cost 3D Memory With DBI® Wafer Bonding and Interconnect Technology

Ability to Replace Die Stacking with High-strength Wafer Stacking

Simplifies Process Flows, Increases Interconnect Densities

ECTC 2012

SAN DIEGO--()--A new customer collaboration at Ziptronix Inc., the leading developer of direct bonding technology for advanced semiconductor applications, is showing strong potential for major cost savings in 3D memory applications, by replacing standard die-stacking methods with Ziptronix DBI® wafer-stacking technology. Ziptronix made the announcement at the 62nd Electronic Components and Technology Conference (ECTC) in San Diego.

Memory stacking is one of the most intriguing applications of 3D integrated circuit technology, as it has the potential to enable much higher memory density in a given footprint. But to date, process costs have been high, driven by the challenges of die thinning, handling of the thinned dies, and development of reliable interconnect processes.

Ziptronix DBI®, which combines proprietary wafer-level low-temperature oxide bonding and interconnection, is showing substantial cost reductions in customer-driven development work focused on server and portable memory applications. That work is now moving into the prototype evaluation stage.

DBI® has been proven in the backside imaging (BSI) sensor marketplace, another cost-sensitive sector, and can deliver cost savings of up to 80 percent compared to copper thermo-compression bonding. Because DBI® creates extremely strong low-stress bonds, it allows wafers to be processed and thinned after bonding, greatly simplifying process requirements by eliminating the need to handle thinned wafers and/or dies. In addition, DBI® offers the highest available interconnect density and alignment accuracy, and is fully compatible with damascene interconnect processing, opening new avenues for foundry-based through-silicon via process flows.

Moreover, the uniform, high hybrid bond strength of the DBI® process enables the highest vertical stacking density, and the thinnest overall height of finished 3D devices. It also supports a range of post-bonding test and repair strategies.

“This new collaboration shows that silicon supply chain companies have taken notice of how well our bonding and interconnect technologies are performing in the image sensor space, and that they are eager to utilize Ziptronix processes in other applications,” said Ziptronix CEO Dan Donabedian. “We see great potential for DBI® across the board in 3D, and plan to announce licensing agreements outside the image sensor space later this year.”

About Ziptronix

Ziptronix is a pioneer in the development of low-temperature direct bond technology for a variety of semiconductor applications, including backside-illuminated (BSI) sensors, RF front-ends, pico projectors, memories and 3D integrated circuits. Its patented, scalable 3D-integration technology, including ZiBond® and DBI®, provides the lowest-cost bonding solution for 3D technology, while enabling size reduction, yield enhancement, lower production costs and power consumption, and increased system performance. The company holds more than 39 U.S. patents and more than 25 international patents in nine foreign countries and Europe. It has more than 45 U.S. and international patent applications pending. Ziptronix licenses its technology throughout the semiconductor supply chain, including OEMs, IDMs and some fabrication and assembly facilities, and operates a back-end-of-line R&D facility with 6,000 square feet (557m2) of Class 100/1000 cleanroom space at its headquarters in Research Triangle Park, N.C. Ziptronix was founded in 2000 as a venture-backed spinoff of RTI International.


Sarah-Lyle Dampoux, +33 1 58 18 59 30

Release Summary

Ziptronix and customer pursue lower-cost 3D memory with DBI® wafer bonding and interconnect technology


Sarah-Lyle Dampoux, +33 1 58 18 59 30