Teradyne Japan Hosts Fourth Annual Technical Seminar; Solutions for Improving Test Productivity and Economics

TOKYO--(BUSINESS WIRE)--Dec. 3, 2003--Teradyne's Semiconductor Test Japan Division hosted its fourth annual technical seminar in November with a theme of "Do More For Less." The technical seminar, held at Hotel Intercontinental Tokyo Bay, featured a keynote address by Mr. Keiichi Kawate, President, Representative Director & CEO of Advanced SoC Platform Corp. (ASPLA), speaking on the SoC industry in Japan. One hundred and sixty-two registered attendees participated in fourteen technical seminars on topics which included: Open Architecture - Attributes for Success, Improving the Efficiency of Multi-site Testing Test Efficiency and SoC Device Testing by VHFAC. Six of the technical seminars were presented by four Teradyne Japan users: AKM, Renesas, Sanyo and Toshiba. The Teradyne Japan technical seminar is open to all licensed users of Teradyne semiconductor test systems and software products.

"The exchange of technical information at the seminar on current test techniques is an incredibly valuable resource as companies must "Do More For Less" to stay competitive," said Keiichi Kawate, President, Representative Director & CEO of Advanced SoC Platform Corp. (ASPLA). "The seminar provided the opportunity to share ideas with Teradyne and other Teradyne users that will improve how participants approach test efficiency by establishing common test methodologies."

“By providing a technical seminar focusing on test productivity and test solutions, our customers are able to exchange ideas and benefit from a unique community from which to leverage the industry's best test solutions”

"By providing a technical seminar focusing on test productivity and test solutions, our customers are able to exchange ideas and benefit from a unique community from which to leverage the industry's best test solutions," noted Andy Blanchard, Teradyne Japan Representative Director.

About ASPLA

ASPLA was established in July 2002 with capital investment from 11 member companies on the Japan Electronics and Information Technology Industries Association (JEITA). Our mission is to build and develop the standard process for the 90-nm era on 300mm wafers, and manage the line to verify design IP (Intellectual Property) and SoC. ASPLA develops wafer process technology and standardization, and STARC (the Semiconductor Technology Academic Research Center) develops design methodology and builds libraries and IP. Through collaboration with STARC, we established "SoC Technology Platform", which we will develop a complete and consistent design and manufacturing process for next-generation SoC. ASPLA is a joint venture of 10 of Japan's major LSI makers (Fujitsu, Matsushita, NEC, Oki, Renesas, Rohm, Sanyo, Sharp, Sony, and Toshiba).

About Teradyne

Teradyne (NYSE:TER) is the world's largest supplier of Automatic Test Equipment and a leading supplier of interconnection systems. The company's products deliver competitive advantage to the world's leading semiconductor, electronics, automotive and network systems companies. In 2002, Teradyne had sales of $1.22 billion, and currently employs about 6700 people worldwide. For more information, visit www.teradyne.com. Teradyne is a trademark of Teradyne, Inc. in the US and other countries.