First 65-nm X Architecture Interconnect Test Chip Produced at Applied Materials` Maydan Technology Center

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 25, 2004--

The X Initiative, a semiconductor supply-chain consortium, today announced that Applied Materials, Inc. (Nasdaq:AMAT) has produced the industry's first 65-nm interconnect test chip for X Architecture designs at its Maydan Technology Center in Sunnyvale, Calif. Applied Materials leveraged its wafer fabrication equipment and processes, along with lithography equipment from Canon U.S.A. Inc. and design expertise from Cadence Design Systems, Inc., to produce the interconnect test chip--demonstrating the manufacturability of the X Architecture designs for very advanced copper/low-k chips using existing process technologies.

Applied Materials first fabricated an X Architecture 90-nm interconnect test chip last summer, validating the manufacturability of diagonal interconnect designs at that leading process node. Today's groundbreaking development demonstrates the scalability of the X Architecture into future process generations.

The X Architecture represents a new and more efficient way of orienting a chip's maze of microscopic wires using diagonal pathways, as well as the traditional right angle, or "Manhattan," configuration. By enabling designs with significantly less wire and fewer vias, or connectors between wiring layers, the X Architecture can provide significant improvements in chip performance, power consumption and cost.

Test chips are critical to design for manufacturability because they enable chipmakers to verify the quality and reliability of design rules before manufacturing. The results of this interconnect test chip validate that X Architecture design rules for intermediate metal layers are comparable to those for Manhattan designs.

"Our work with Cadence and Canon on this 65-nm intermediate layer interconnect test chip provides further confirmation of the manufacturing readiness and scalability of X Architecture designs for future process nodes," said John T.C. Lee, general manager of Applied Materials' Maydan Technology Center. "It leverages standard design, verification, mask making, processing, and inspection disciplines into functioning interconnect test structures."

Cadence Design Systems, Inc. provided the test structure design and chip validation tools for the project. Canon's ArF imaging system was employed for the wafer lithography. Applied Materials used its interconnect fabrication technologies to produce the multi-layer copper/low-k interconnect on 300-mm wafers. The results were confirmed using Applied Materials' wafer inspection and metrology systems to validate critical dimension and defect levels.

"Applied Materials, along with Canon and Cadence, are once again leading the industry by proving the manufacturability of the X Architecture at the 65-nm process node, ahead of end-user production lines," said Aki Fujimura, X Initiative steering group member and CTO, new business incubation at Cadence Design Systems, Inc. "Supply chain collaboration through the X Initiative continues to advance the X Architecture as a new production design option."

Those interested in hearing more about the X Initiative are invited to visit X Initiative's booth # 810 at the SPIE Microlithography Conference, February 24 - 25, 2004 at the Santa Clara Convention Center in Santa Clara, Calif. In conjunction with the conference, two papers will be presented at SPIE on Thursday, February 26 from 10:20 a.m. - 12:20 p.m., which will provide more details on the fabrication of the 90-nm and the 65-nm test chips. These papers are titled: "Manufacturability of the X Architecture at the 90-nm technology node" (5379-06) M. C. Smayling, Applied Materials, Inc.; R. C. Sarma and N. Arora, Cadence Design Systems, Inc., and "Taking the X Architecture to the 65-nanometer technology node" (5379-07) R. C. Sarma and N. Arora, Cadence Design Systems, Inc.; M. C. Smayling, Applied Materials, Inc.

About Applied Materials

Applied Materials, Inc. (Nasdaq: AMAT) is the largest supplier of equipment and services to the global semiconductor industry. Applied Materials' Web site is http://www.appliedmaterials.com

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20 percent and via-counts by more than 30 percent, resulting in simultaneous improvements in chip performance, power and cost. For the past 20 years, chip design has been primarily based on the de facto industry standard "Manhattan" architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative's five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon supply chain, X Initiative members include: Applied Materials, Inc.; ARM; Artisan Components, Inc.; ASML Netherlands B.V.; Cadence Design Systems, Inc.; Dai Nippon Printing (DNP); DuPont Photomasks, Inc.; Etec Systems, Inc., an Applied Materials, Inc. company; GDA Technologies, Inc.; HPL Technologies, Inc.; Hoya Corporation; IN2FAB Technology Ltd.; Infineon Technologies AG; JEOL, Ltd.; KLA-Tencor Corporation; Leica Microsystems AG; Matsushita Electric Industrial Co., Ltd.; MicroArk Co. Ltd.; Monterey Design Systems, Inc.; Nikon Corporation; NuFlare Technology Inc.; PDF Solutions, Inc.; Photronics, Inc.; Prolific Inc.; RUBICAD Corporation; Sagantec; Sanyo Electric Co., Ltd.; Silicon Logic Engineering, Inc.; SiliconMap, LLC.; Silicon Valley Research Inc.; STMicroelectronics; Sycon Design, Inc.; Tensilica, Inc.; Toppan Printing Co.; Toshiba Corporation; Trecenti Technologies, Inc.; UMC; Virage Logic, Inc.; Virtual Silicon Technology, Inc.; and Zygo Corporation. Membership is open to all companies throughout the semiconductor supply chain. Materials can be found at www.xinitiative.org

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current technology, the future success of X Architecture technology and the ability of certain of the X Initiative members to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements' current expectations. Actual results and events may differ materially due to a number of factors including, among others: future strategic decisions made by the X Initiative members; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members, individually or collectively, assume no obligation to update the forward-looking information contained in this release.