Teradyne and Mentor Graphics Partner to Bridge the Design-to-Manufacturing Test Gap

BALTIMORE--(BUSINESS WIRE)--Oct. 29, 2001--Teradyne (NYSE: TER) and Mentor Graphics Corporation announced a partnership aimed at speeding time-to-market, reducing test costs and improving yields of semiconductors tested with Design-for-Test (DFT) techniques. The two companies will bridge the gap between IC design and manufacturing test by creating a range of new tools and links between Mentor's DFT products used in design and Teradyne's automatic test equipment (ATE). The initial phase will center on providing a complete solution for rapid failure diagnosis by linking the Mentor Graphics(R) FastScan(TM) software diagnostics tool and Teradyne ATE, including the J973 and J750 VLSI testers and Catalyst and Tiger test systems. A preview demonstration of the failure diagnosis link being developed will be shown in the Teradyne booth at the International Test Conference, October 30 to November 1, 2001 in Baltimore, Maryland.

Shrinking semiconductor device sizes, the increasing number of metal interconnect layers and the continuing adoption of DFT methods like scan strengthens the role of DFT-based failure analysis in improving yield and time-to-volume. High transistor count VLSI designs and new semiconductor process technologies are particularly good candidates to benefit from this method. But the gap between design and manufacturing test places major hurdles in front of semiconductor companies seeking to fully leverage DFT tools for fast, effective failure diagnosis. Currently, there are no robust solutions available to feed tester-produced data to DFT diagnostic tools. Complementary analytical tools to identify the dominant failures and faults are also lacking. This considerably restricts the efficiency and capability of DFT-based failure diagnosis.

The Teradyne-Mentor failure diagnostics flow will provide a direct solution to the need for "software-based fault localization tools compatible with major test methodologies such as scan," as described in the International Technology Roadmap for Semiconductors (ITRS), published by the Semiconductor Industry Association. This new integrated solution will provide a complete test-to-diagnosis flow that significantly reduces the cycle time required to isolate defects on failing components. This tool will greatly simplify and automate the process of analyzing tester data, feeding directly into FastScan Diagnostics for identification of the precise failing node and discovering the most common defects causing yield problems.

"The FastScan Diagnostics-Teradyne flow is an excellent example of Mentor's ability to collaborate and develop solid solutions to meet designer's needs in the manufacturing test arena," said Lori Watrous-deVersterre, general manager of the Mentor Graphics Design-for-Test division. "By offering a wide range of test solutions, we can work with partners such as Teradyne to further extend automation and vastly improve manufacturing test for our mutual customers."

"The design-to-test gap is widest in the failure analysis and diagnosis area," explained Marc Levine, vice president, Teradyne. "The more DFT is used by our customers, the more critical it becomes to provide a cohesive environment that integrates our testers and design tools, beginning with the defect isolation process. This partnership with Mentor Graphics demonstrates Teradyne's commitment to provide leadership in helping our customers leverage test methodologies like DFT to realize new efficiencies and lower test costs."

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 2,975 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

About Teradyne

Teradyne (NYSE: TER) is the world's largest supplier of automatic test equipment and is also a leading supplier of high performance interconnection systems. Manufacturers of semiconductors, circuit assemblies, and voice and broadband telephone networks use Teradyne's test products. Manufacturers of communications and computing systems central to building networking infrastructure use Teradyne's backplane assemblies and high-density connectors. The company had sales of $3.0 billion in 2000 and currently employs about 8000 people worldwide. For more information visit www.teradyne.com.

Mentor Graphics is a registered trademark of Mentor Graphics Corporation. FastScan is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

“By offering a wide range of test solutions, we can work with partners such as Teradyne to further extend automation and vastly improve manufacturing test for our mutual customers.”