Hynix Semiconductor and Teradyne Demonstrate 125 MHz DRAM Wafer Test for Bare Die; Wafer to Package Correlation Paves Way for New DRAM Applications

AGOURA HILLS, Calif.--(BUSINESS WIRE)--July 13, 2001--Hynix Semiconductor, Inc., has recently evaluated high-speed wafer test at its facility in Ichon, Korea. This evaluation, conducted on a Teradyne J996FA 125 MHz wafer probe system, was done to lay the groundwork for expanded sales of DRAM bare die and increasing use of wafer-level chip scale package (CSP) applications.

Bare die chips are unpackaged devices typically used in Multi-Chip Modules (MCM) for communication and consumer applications such as next generation cell phones, PDA's, and digital cameras. Semico Research in Phoenix Arizona predicts that DRAM consumption in the digital communications and consumer application will grow at nearly double the rate of the computer related applications over the next few years, achieving nearly 55% of the DRAM market by 2005. These applications demand the ultimate in miniaturization, which is made feasible with the use of MCMs and CSPs.

"Today most DRAM bare die are sold without being tested at full array speed," said Joo Young Lee, Memory Product Manager, Teradyne Inc. "Test speed at wafer probe has been limited to 60 MHz or less by insufficient timing accuracy, along with narrow probe card bandwidths and interface technologies that hinder signals between the channel card and wafer." However, testing at such low frequency does not guarantee that a device will perform correctly in the final application, resulting in high failure rates for the assembled final product.

"The J996FA with its high-bandwidth interface and FormFactor probe cards has successfully demonstrated that it can test die at full 125 MHz array speeds," said Dr.J.S. Kih, director of Product Engineering, Hynix Semiconductor Inc. "Engineering measurement of timing parameters at wafer probe correlated with that of package test well within the device margin, meaning that we can guarantee that our bare die achieve full functional specification. Ultimately, when wafer burn-in is available, package test could be completely eliminated."

"We have thought for some time now that memory device manufacturers would move more of their testing from package to probe testing," said Harold Labonte, Memory Marketing Manager, Teradyne, Inc. "These results pave the way for that migration. The engineering work done at Hynix demonstrates that the J996FA system can meet the needs of memory devices with array speeds up to 125 MHz. The recently introduced Probe-One Memory Test System will handle tomorrow's devices with array speeds up to 250 MHz." It is estimated that from 70 to 90 percent of testing done at package today is array testing, and these tests are candidates for a move to wafer probe. This migration will be accelerated by the need to keep costs at a minimum as the communication and consumer applications become dominant segments of the DRAM market.

About Teradyne

Teradyne (NYSE:TER) is the world's largest supplier of automatic test equipment and is also a leading supplier of high performance interconnection systems. Teradyne's test products are used by manufacturers of semiconductors, circuit assemblies and voice and broadband telephone networks. Teradyne's backplane assemblies and high-density connectors are used by manufacturers of communications and computing systems central to building networking infrastructure. The company had sales of $3 billion in 2000 and currently employs about 9000 people worldwide. For more information visit www.teradyne.com.

“Engineering measurement of timing parameters at wafer probe correlated with that of package test well within the device margin, meaning that we can guarantee that our bare die achieve full functional specification. Ultimately, when wafer burn-in is available, package test could be completely eliminated.”