Catalyst Family Expands Digital, Bluetooth Wireless Technology, and Parallel Cell Test Capabilities

BOSTON--(BUSINESS WIRE)--July 7, 2000--Teradyne, Inc. (NYSE: TER) broadens the market-leading Catalyst system-on-a-chip (SOC) tester family with showings at the industry trade show Semicon West to be held July 12 - 14 in San Jose, CA. Demonstrations include focused discussions around wireless and high-speed data link test as well as the first public look at the new Catalyst Tiger, a 1024 pin / 1.6 Gbps SOC test system.

Catalyst showcases Bluetooth(TM) wireless device testing with Teradyne's MicroWAVE6000(TM) instrumentation suite designed for the high growth cellular phone market and new wireless communications standards. Also showing will be high-speed serializer/deserializer (SERDES) device testing with the Catalyst gigabit differential digital option, Gazelle.

Catalyst Tiger is the first SOC test system to break the 1 Gbps barrier. The same Zero Time DSP architecture that makes Catalyst the world SOC test economic leader enables Tiger to easily handle quad and octal site test for new one chip / one product SOC devices. Aimed initially at high pin count chipset and network switching devices, Tiger sets the new standard for SOC test: 1024 single ended or differential pins, device focused programming with timing, format, and I/O changes at full speed, integrated precision analog, ultra low jitter clocks, and high-speed time digitizing on any pin.

About the Catalyst Family

The leading system-on-a-chip test system with more than 700 systems booked worldwide, Catalyst tests DSL, set top box, DVD, cellular, graphics, LAN, power management, PRML, and microwave devices.

The Catalyst SOC test family reduces time-to-market and test cost through state-of-the-art instrumentation, including the MicroWAVE6000, Gazelle, 1.5 ps jitter PicoClock(TM), and the new Time Jitter Analyzer with 5 ps jitter high speed time sampling instrumentation. Catalyst digital is available from 25 MHz to 1600 Mbps I/O and from 16 to 1024 pins to match wide device needs and parallel test configurations.

Catalyst Tiger is an extension of the Catalyst family for high performance, high pin count, or high parallel site count applications. Breakthrough Silicon Germanium (SiGe) technology provides high data rate, full I/O, and timing changes on the fly at top speed required for chipset, networking, and disk SOC devices.

With IMAGE(TM) test engineering software linked to design through VX software, Catalyst users enjoy a comprehensive development environment. VX qualifies the device design model and test methods before first silicon by closing the loop between design and test simulation. IMAGE provides a template driven programming environment for test IP portability and also includes direct hardware control for custom method authoring. Full parallel test support combined with a unique parallel processing background DSP environment speeds production throughput, improving capital utilization. Coupled with multiple time domain operation in Catalyst, IMAGE now introduces parallel cell test, asynchronous test within the IC itself, driving test time down even further.

About Teradyne

Teradyne is the world's largest supplier of automatic test equipment and related software for the electronics and telecommunications industries and a leading supplier of high-performance backplane assemblies and connectors. Teradyne supports its products through an extensive service and applications engineering network, with technical centers located throughout the United States, Europe, and the Pacific Rim. Headquartered in Boston, Massachusetts, Teradyne reported sales of approximately $1.8 billion in 1999 and currently has about 8,000 employees worldwide. Teradyne's World Wide Web address is http://www.teradyne.com.

PicoClock, IMAGE and MicroWAVE6000 are trademarks of Teradyne, Inc. Bluetooth is a trademark owned by Telefonaktiebolaget LM Ericsson, Sweden.