"Today, it's all about speed -- data speed and test speed," said Brad Robbins, Teradyne, General Manager, Industrial/Consumer Division. "Internet and wireless communications continue to push data rates up. Speeds routinely exceed a gigabit per second and there is no end in sight. To meet the new digital consumer price points, manufacturers need cost-effective test. Catalyst and Tiger use a unique parallel processing architecture to achieve higher test speed, dramatically driving down test time, lowering SOC test costs. More parts per hour, fewer testers. It's really that simple," continued Robbins.
IBM's Silicon Germanium (SiGe) -- New Technology for The Internet Era Tiger's timing system architecture combines custom high-density CMOS for flexibility and high-performance IBM Silicon Germanium (SiGe) for final timing generation to create breakthrough digital test speeds. The CMOS / SiGe combination creates an unmatched range from full timing flexibility for wide data busses to high speed differential for new multi-gigabit communications links. Flexible waveform capability allows multiple independent time domains with edge timing, wave shape, and period switching on-the-fly at full data rates. This innovative SiGe / CMOS approach thus enables Device Under Test (DUT)-cycle programming, where test waveforms are based on DUT timing needs and not constrained by a tester's instruction cycle rate.
SOC Tester in a Test Head
Tiger integrates 1024 complete digital channels into the compact test head. Each 32 channel test head card contains per pin resources including PMUs, pin electronics, pattern memory, and timing system. Scan, memory test, and digital signal source and capture are also on each card, allowing parallel test up to 32 sites.
Catalyst Proven Analog
Tiger features the proven Catalyst instantaneous analog instrumentation with zero-time FlexDSP(TM) architecture and full differential I/O. Immediately available options include audio, video, DSL, cable modem, and wireless test instruments as well as the industry leading 2.5 gigasample 10- bit waveform generator and digitizer for 100/1000baseT networking applications. Ultra low jitter clocks and a high speed Time Jitter Analyzer provide gigaHertz performance for converter and phase locked loop testing.
Software Scaled Digital
Catalyst Tiger is the first system silicon test system to offer complete software-only performance upgrades from 300 MHz to 1.6 Gbps. Each 32 pin slice can be licensed at a different speed allowing tester optimization for devices with wide/slow and narrow/fast busses. This 'inventory on board' approach provides the unmatched flexibility and longer capital life IC manufacturers and subcontractors demand.
Price and Delivery
U.S. pricing for the Catalyst family runs from under $1,000,000 for mixed signal applications to approximately $3 million for high performance multi- site testers. Catalyst is shipping in record numbers today with Tiger deliveries scheduled to begin in the fourth quarter of 2000.
About Teradyne
Teradyne is the world's largest supplier of automatic test equipment and related software for the electronics and telecommunications industries and a leading supplier of high-performance backplane assemblies and connectors. Teradyne supports its products through an extensive service and applications engineering network, with technical centers located throughout the United States, Europe, and the Pacific Rim. Headquartered in Boston, Massachusetts, Teradyne reported sales of approximately $1.8 billion in 1999 and currently has over 7,200 employees worldwide. Teradyne's World Wide Web address is http://www.teradyne.com.
Catalyst and FlexDSP are trademarks of Teradyne, Inc.
“Today, it's all about speed -- data speed and test speed”

