Gen-Z Consortium Signals Continued Growth with Multi-Vendor Demo and Specifications Progress at SC’17

Gen-Z Scalable Connector Specification 1.0 Released

DENVER--()--The Gen-Z Consortium, an organization developing an open systems interconnect designed to provide high-speed, low latency, memory-semantic access to data and devices, today shared that it will show a Gen-Z multi-vendor technology demonstration connecting compute, memory, and I/O devices at the 2017 Super Computing Conference (SC’17), taking place this week in Denver, Colorado. The multi-vendor technology demonstration utilizes FPGA-based Gen-Z adapters connecting compute nodes to memory pools through a Gen-Z switch, creating a fabric that connects multiple server vendors and a variety of memory vendors.

The Gen-Z Consortium has made significant progress in its first year, more than doubling its membership since 2016 to nearly 50 companies. Recent accomplishments include the creation of the FPGA-based demo, the release of the Gen-Z Scalable Connector Specification, and contribution of the mechanical and electrical specification of its scalable connector to SNIA/SFF.

The Gen-Z Scalable Connector Specification 1.0 defines a high density solution (with a 0.6 mm pitch) that minimizes board space consumption. The three connector sizes will provide 8, 16 or 32 differential pairs in vertical and right angle implementations and will enable solutions to scale from 2.5GT/s NRZ to 112 GT/s PAM 4 signaling. The scalable connector will also support cable solutions for both copper and optical implementations. The Gen-Z Consortium looks forward to working with SNIA/SFF and other industry standards groups to enable broader use of this cutting edge connector.

The Consortium is currently preparing for the release of the Gen-Z Core Specification. The specification is in its final review cycle among its members and is set for 1.0 release to member companies in December 2017 and public availability in January 2018. The release will allow members to finalize their plans for silicon enablement.

“We’re so grateful to our member companies that have spent the last year working diligently to shape Gen-Z’s memory-centric standards-based approach and achieve tangible milestones,” said Kurtis Bowman, President of the Gen-Z Consortium. “The Consortium continues to grow and we encourage interested companies to join us as we work toward developing the future of data centers.”

Gen-Z Consortium at SC’17

Visit the Gen-Z Consortium in booth #992 at SC’17. Michael Krause, HPE VP and Fellow, will present “Understanding Gen-Z Technology – A High Performance Interconnect for the Data-Centric Future” on Tuesday, Nov. 14 at 2:30pm in room 503-504.

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About Gen-Z Consortium

Gen-Z is an open systems interconnect designed to provide memory semantic access to data and devices via direct-attached, switched or fabric topologies. The Gen-Z Consortium is made up of leading computer industry companies dedicated to creating and commercializing a new data access technology. The Consortium’s 12 initial members were; AMD, ARM, Broadcom, Cray, Dell EMC, Hewlett Packard Enterprise, Huawei, IDT, Micron, Samsung, SK hynix, and Xilinx with that list expanding as reflected on our Member List.

The Gen-Z Consortium strongly believes in developing an open ecosystem where members, the broader industry, and customers can work together to deliver robust, high-quality specifications that meet solution needs. The Gen-Z Consortium will periodically publicly post draft specifications and technical concepts to elicit input from the broader industry and directly from customers. For more information visit www.genzconsortium.org.

Contacts

Nereus for Gen-Z
Rachael Watson, 971-706-1312
rwatson@nereus-worldwide.com

Release Summary

Gen-Z Consortium will show a Gen-Z multi-vendor technology demo connecting compute, memory, and I/O devices at SC17 in Denver, Colorado.

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Contacts

Nereus for Gen-Z
Rachael Watson, 971-706-1312
rwatson@nereus-worldwide.com