Flip Chip/WLP Manufacturing and Market Analysis Report 2017-2018 - Research and Markets

DUBLIN--()--The "Flip Chip/WLP Manufacturing and Market Analysis" report has been added to Research and Markets' offering.

The Number of Packages Utilizing WLP Will Equal Flip Chip Shipments in 2018 And Then Continue Growing at a CAGR of 15%

Flip Chip/WLP Manufacturing and Market Analysis, the number of packages utilizing WLP will equal Flip Chip shipments in 2018 and then continue growing at a compound annual growth rate of 15% (between 2014 and 2020) compared to just 5% for Flip Chip, as shown in the graphic below.

Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT. Flip chip technology is slowly replacing wire bonding for many high-performance chips. Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA).

This technology can be applied on application processor, baseband, PMIC, memory devices, etc. products. For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets.

Fan-out WLP (FO-WLP) enables redistribution of I/Os beyond the chip footprint, differing from Fan-in WLP in several key areas. The FO-WLP process typically starts when individual dies are placed on double-sided tape sitting on a silicon carrier. The die is covered with a mold compound, and the carrier and tape are removed, leaving the die embedded in the mold. The wafer is turned over; an RDL is created, and solder balls are formed on top, just as in a Fan-in WLP. The extra panel surface area around the chip permits I/Os to be both fanned in over the chip and fanned out across the mold compound, making it possible to accommodate a larger number of I/Os.

One major advantage of FO-WLP, especially in mobile applications, is that the elimination of the substrate reduces the vertical footprint by an average of 40% compared with Fan-in WLP, enabling thinner products or making it possible to stack more components in the same form factor. The elimination of the interposer and TSVs also provides a cost reduction and eliminates concerns on the effects of TSVs on electrical behavior. The reduced path to the heat sink also helps improve thermal performance.

Key Topics Covered:

Chapter 1 Introduction

Chapter 2 Executive Summary

Chapter 3 Flip Chip/WLP Issues and Trends

Chapter 4 Lithography Issues And Trends

Chapter 5 UBM Etch Issues And Trends

Chapter 6 Metallization Issues and Trends

Chapter 7 Market Analysis

Companies Mentioned

  • Advanced Micro Devices, Inc.
  • Amkor Technology
  • ASE Group
  • Cisco
  • EV Group
  • IBM Corporation
  • Intel
  • Intel Corporation
  • Jiangsu Changjiang Electronics Technology Co. Ltd.
  • On Semiconductor
  • Qualcomm Technologies, Inc.
  • Rudolph Technology
  • SAMSUNG Electronics Co. Ltd.
  • Siliconware Precision Industries Co., Ltd.
  • Sony Corp
  • STMicroelectronics
  • SUSS Microtek
  • Taiwan Semiconductor Manufacturing Company
  • Texas Insruments
  • Tokyo Electron
  • TSMC

For more information about this report visit https://www.researchandmarkets.com/research/56q9xc/flip_chipwlp

Contacts

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Related Topics: Semiconductor

Contacts

Research and Markets
Laura Wood, Senior Manager
press@researchandmarkets.com
For E.S.T Office Hours Call 1-917-300-0470
For U.S./CAN Toll Free Call 1-800-526-8630
For GMT Office Hours Call +353-1-416-8900
Related Topics: Semiconductor