AUSTIN, Texas--(BUSINESS WIRE)--Silicon Integration Initiative Inc. (Si2), a research and development joint venture, announced today the contribution of a new integrated circuit programming language developed by Intel Corporation (NASDAQ: INTC) for the 2D pattern analysis of sub-20nm mask layouts.
The new language, called OPAL (Open Pattern Analysis for Layout), is a declarative language for geometric pattern matching. “It’s a high-level, modeling language that can describe layout patterns of any complexity,” according to Jake Buurma, an Si2 senior fellow. “OPAL provides an essential set of geometric expressions that can find specific patterns that detract from yield and it can find the robust patterns that improve first-pass yield over normal manufacturing variances.”
For example, in sub-20nm processes, wires used for interconnect have an ideal pitch for the mask to chip image transfer during lithography, Buurma explained. “But these wires also have a prohibited pitch where the image transfer is poor since lithography cannot faithfully reproduce certain 2D patterns. The OPAL language searches for the layout patterns of both yield detractors and yield enhancers and then back annotates markers onto those patterns that will have an impact on manufacturing yield.”
“At Intel, we’ve been developing layout modeling languages for over 10 years and OPAL is our latest modeling advancement which is capable of describing any geometric constraint regardless of complexity and has the potential to automatically create test layout, runsets, and tool models,” said Ramond Rodríguez, director, Strategic CAD Capabilities at Intel. “Along with several technology contributions Intel has made to Si2 which extend the Si2 OpenAccess database, we’re excited that OPAL can leverage some of our prior contributions, such as oaxPOP, which is a geometric engine for polygon operators on OpenAccess.”
“OpenAccess has always had the ability to store mask layout constraints in its C++ database, but the actual checking of those constraints required an expert to program an exact sequence of steps into a design rule checking engine,” Buurma said. “But as a high-level, declarative language, OPAL can model complex 2D patterns by just describing a specific pattern with a few geometric expressions.”
Si2 will host the OPAL project and launch an OPAL Working Group to evaluate and entertain proposals for an industry roadmap on how to best utilize the newly contributed technology from Intel.
Gyuszi Suto, principle engineer at Intel and the lead developer of OPAL, said that “Working with an R&D joint venture is the best way for a team of experts, like an Si2 Working Group, to specify a standard methodology that allows users to clearly and concisely write geometric searches that find specific 2D patterns in their layouts.”
At DAC 2017, Si2 will hold an OPAL workshop where a team of industry experts will describe the rapidly growing number of layout and pattern constraints that appear at sub-20nm manufacturing nodes. The complimentary workshop will be held Monday, June 19, 11:00 a.m. – 1:00 p.m., in Room 7 at the Austin Convention Center. For reservations visit http://www.si2.org/events/opal/.
For more information about this project, contact Jake Buurma at JakeBuurma@si2.org.
Si2 is holding a number of other DAC events, including the latest innovations in application of the OpenAccess database, training on use of the scripting interface to OpenAccess, and the latest developments in system-level power modeling. For more information visit: http://www.si2.org/dac-2017
Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers and EDA companies.