Sarcina Technology LLC Introduces a Technology Licensing Program for 25G+ Serializer/Deserializer (SerDes) Package Design

PALO ALTO, Calif.--()--Today Sarcina Technology LLC (“Sarcina”) introduces a technology transfer licensing program for 25G+ Serializer/Deserializer (SerDes) Package Design for use in high speed data communication chips in the data center and cloud computing markets. Sarcina remains committed to advancing the package design knowledge of the semiconductor industry by sharing its research with interested companies through this technology transfer program.

Today impedance mismatch of package vertical interconnection caused by BGA ball, Plated-Through -Hole (PTH), and Via has become the bottleneck of a BGA package for 25G+ SerDes communication. Because BGA is the only viable package type for high pin count I/O packages and SerDes (including PCIe, SATA, SAS, et al) is the dominate chip-to-chip I/O protocol for high data rate communication, overcoming this bottleneck is highly desirable. Ten years ago when the 10G SerDes emerged as the standard for backplane communication, people started to notice this impedance mismatch problem. By creating a small ground void around a SerDes vertical interconnection, manufacturers were able to control the impedance variation to within ±10%. Now at 25G+ data rate, engineers at major semiconductor companies are working diligently to tackle this problem. Unfortunately, conventional methods can no longer solve this problem. Even worse, with the rise time as low as 8 ps, the impedance mismatch mushrooms to as high as ±35%. This creates a high return loss and signal reflection and not only degrades signal amplitude but also brings in undesired reflected noise. As a result, the eye height of the receiving signal is squeezed down.

Sarcina has solved this problem with a package design that employs unique, inexpensive structures and methods that allow the impedance mismatch to be controlled again to less than ±10% even for a 12 layer package buildup substrate. As a result, the eye height can be enlarged by nearly 20%.

Larry Zu, Ph.D., President of Sarcina Technology LLC comments: “Combining the chip technologies of pre-emphasis, equalization and automatic adaptation with our package design technology, the signal transmission distance and quality could be significantly enhanced for 25G+ SerDes."

"This new technology does not increase package substrate cost as it utilizes the standard package design rules. It does not require any new processes in substrate fabrication and package assembly. Also, it does not add any additional processing steps. Therefore, there is no cost increase in assembly.”

“In addition to the vast majority of NRZ (Non-Return-to-Zero, or PAM-2) applications, this technology should be especially beneficial to the PAM-4 (Pulse Amplitude Modulation) communication mechanism. Since PAM-4 cuts the amplitude to 1/3 of a PAM-2 (NRZ) signal, the requirement for SerDes impedance mismatch and return loss should be more stringent. Our packaging technology could be a right fit to PAM-4.”

“Besides ASIC chips, this technology should also be useful to the new memory chips which utilize SerDes as its I/O protocol. With Through Silicon Via (TSV) enabled memory stacking technology going into production, SerDes has started to replace parallel DDR interconnections for high-end memory chips. Today’s Hybrid Memory Cube (HMC) version 2.0 uses 15 Gb/s SerDes as its I/O for data transmission. The next HMC version 3.0 will run at 30 Gb/s. This is the speed where our technology could contribute.”

To benefit all semiconductor companies working on 25G+ SerDes, Sarcina has structured the technology transfer program with very favorable terms.

Companies interested in the technology transfer program and learning more about the detailed benefits of this technology may visit sarcinatech.com. Further, companies interested in discussing a license with Sarcina Technology LLC for this technology are kindly requested to send an e-mail to info@sarcina-tech.com.

About Sarcina Technology LLC

Founded in 2011, Sarcina Technology is a semiconductor packaging company in Palo Alto, California, USA with a design office in Hsinchu, Taiwan. It is led by industrial veterans from places like AT&T Bell Labs, DEC, Intel and TSMC. Sarcina Technology provides leading US companies with package design and power/signal integrity simulation. In addition, Sarcina offers final test hardware design, program development, and one-stop turnkey service. We work with the world's foremost foundries to ensure high quality products. We've handled everything, from the simplest to the most complex of packages. Our results are self-evident: since its formation, Sarcina's tapeouts have all been first-time successes.

Contacts

For press inquiries please contact:
Sarcina Technology LLC
Larry Zu, +1 408-667-2869
Larry.Zu@sarcina-tech.com

Contacts

For press inquiries please contact:
Sarcina Technology LLC
Larry Zu, +1 408-667-2869
Larry.Zu@sarcina-tech.com