LOUISVILLE, Colo.--(BUSINESS WIRE)--The Design and Verification Conference (DVCon), sponsored by Accellera Systems Initiative, concluded this week with record numbers in attendance, as well as a sold out exhibit floor.
Overall attendance, including exhibit-only and technical conference attendees, was 932. Attendance was further enhanced by 281 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,213 participants. The conference attracted 36 exhibitors, including 10 exhibiting for the first time and 6 of them headquartered outside of the US.
The Award for Best Paper Presentation, as voted by conference attendees, went to Ram Narayan and Tom Symons with Oracle Labs, for their presentation titled, “I Created the Verification Gap.” Two Honorable Mentions were also recognized: “Mining Coverage Data for Test Set Coverage Efficiency,” by Monica C. Farkash and Balavinayagam Samynathan, University of Texas at Austin, and Bryan Hickerson and Michael Behm, IBM Corp. and “Lies, Damned Lies, and Coverage,” by Mark Litterick, Verilab, Inc.
Best Poster Presentations were awarded for the third year. Top honors went to Jeremy Ridgeway, Avago Technologies for his poster, “Randomizing UVM Config DB Parameters.” Two Honorable Mentions were also recognized: “SystemVerilog Constraint Layering via Reusable Randomization Policy Classes,” by John Dickol, Samsung Austin R&D Center and “Versatile UVM Scoreboarding,” by Jacob S. Andersen, Peter Jensen and Kevin K. Steffensen, SyoSil ApS.
“DVCon has become the must-attend conference in the design and verification community for networking, technical discussion and learning opportunities,” stated Yatin Trivedi, DVCon General Chair. “From the exhibit floor to the panels, tutorials and poster sessions, there are plenty of opportunities for practicing engineers to learn about new products and share ideas. There is tremendous interest in the content presented at DVCon, so Accellera has expanded DVCon to serve the global community. We look forward to our conferences in Europe and India later in the year.”
“The technical program this year was remarkable,” commented Ambar Sarkar, Ph.D., DVCon Program Chair. “Attendees have come to expect a high quality selection of papers and posters, and we were able to deliver just that. We consistently receive more submissions than we can accept, so we pick the best of the best for our attendees.”
Highlights of the Week:
Aart de Geus, Chairman and co-CEO of Synopsys, delivered an insightful keynote on Tuesday to a standing-room only audience of more than 350 attendees that outlined the business and technology trends that are requiring smart design from silicon to software, made possible via a 'shift left' approach in design, verification, IP and software.
Accellera Day kicked off the conference on Monday. Justin Refice, a Senior Verification Engineer at NVIDIA, was recognized during the Accellera-sponsored luncheon as the recipient of the fourth annual Accellera Technical Excellence Award. He is a member of the UVM™ Working Group.
The DVCon Steering Committee values all feedback regarding the conference. Attendees have been given a survey and are asked to provide input on how to make DVCon 2016 even better.
Save the date: DVCon US 2016 will be held February 29 - March 3, 2016 at DoubleTree Hotel in San Jose, CA. DVCon India 2015 will be held September 10-11 in Bangalore, India and DVCon Europe 2015 will be held November 11-12 in Munich, Germany.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. For more information about DVCon, please visit www.dvcon.org. Follow @dvcon on Twitter or to comment, please use #dvcon.