ARLINGTON, Va.--(BUSINESS WIRE)--JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD229-2 Wide I/O 2. Wide I/O 2 offers a significant speed increase over Wide I/O, while retaining Wide I/O’s vertically stacked through silicon via (TSV) architecture and optimized packaging. Combined, these characteristics position Wide I/O 2 to deliver the ever-increasing speed, capacity, and power efficiency demanded by mobile devices such as smartphones, tablets and handheld gaming consoles. JESD229-2 may be downloaded free of charge from the JEDEC website at http://www.jedec.org/standards-documents/results/jesd229-2.
Wide I/O 2 provides four times the memory bandwidth (up to 68GBps) of the previous version of the standard, but at lower power consumption (better bandwidth/Watt) with the change to 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 die is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint.
Hung Vuong, Chairman of the JC-42.6 Subcommittee for Low Power Memories, noted, “Wide I/O 2 mobile DRAM is an extension of the breakthrough technology pioneered with the publication of Wide I/O in 2012.” Just as switching to multicore processors significantly increased overall computer speed without the need to jump to a new process node, so the vertically stacked architecture allows the Wide I/O 2 interface to deliver four times the bandwidth of LPDDR4 DRAM for around one quarter of the I/O speed.
“With the recent publication of LPDDR4, these two new standards from JEDEC offer designers a range of mobile memory solutions, allowing for maximum flexibility,” Vuong said. “Designers working with a horizontal architecture can choose LPDDR4, while those working with a vertical architecture are supported by Wide I/O 2. In either case, the committee worked to deliver the memory performance that the market requires.”
Mian Quddus, Chairman of the JEDEC Board of Directors, added, “The mobile revolution is driving an unprecedented need for storage solutions that will support the demand for high performance, responsive devices that use less power in a smaller form factor.” He added, “JEDEC’s JC-42.6 Subcommittee is dedicated to providing a range of mobile memory solutions to meet industry needs now and in the future.”
- Number of channels: 4 and 8
- Number of banks: 32 per die
- Density: 8 Gb to 32 Gb
- Page size: 4 KB (4-channel die), 2 KB (8-channel die)
- Max bandwidth per die: 34 GB/s (4-channel die) & 68 GB/s (8-channel die) respectively
- Max I/O speed: 1066 Mbps, 800 Mbps & 1066 Mbps speed bin defined
- Operating Supply Voltage: 1.1V
JEDEC Mobile Forum & LPDDR4 Workshop
To facilitate understanding and adoption of the Wide I/O 2 and LPDDR4 standards, JEDEC is hosting a Mobile Forum and LPDDR4 Workshop in Santa Clara, CA on September 22 & 23, 2014. For online registration and agenda information visit: http://www.jedec.org/CA-2014.
About Wide I/O
Wide I/O mobile DRAM enables chip-level three dimensional (3D) stacking with through silicon via (TSV) interconnects and memory chips directly stacked upon a system on a chip (SoC). JEDEC Wide I/O standards define features, functionalities, AC and DC characteristics, and ball/signal assignments. Wide I/O is particularly well-suited for applications requiring extreme power efficiency and increased memory bandwidth, such as advanced gaming with 3D graphics, HD video, and running multiple applications simultaneously.
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing nearly 300 member companies work together in 50 JEDEC committees to meet the needs of every segment of the industry, manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for free download from the JEDEC website. For more information, visit www.jedec.org.