Research and Markets: Reverse Costing Analysis Report on the Rohm DC/DC Micro Converter TDK-EPC Embedded Die Process

DUBLIN--()--Research and Markets (http://www.researchandmarkets.com/research/x3mcbx/rohm_dcdc_micro) has announced the addition of the "Rohm DC/DC Micro Converter TDK-EPC Embedded Die Process Reverse Costing Analysis" report to their offering.

Rohm and TDK-EPC have joined forces to provide an alternative solution for embedded die technology. This SiP module is a second-source supply of the Texas Instruments MicroSiPDC-DC Converter. Although fully compatible, the process and cost structure is very different from the previously analyzed TI module with a packaging performed by AT&S.

Embedded die packaging is an emerging solution to increase the integration in mobile products. This technology is supported by a game-changing, low-cost, panel-based PCB infrastructure that has the potential to create an alternative supply chain for today's well established packaging standards.

This report provides complete teardown of the Embedded die package with:

- Detailed photos

- Material analysis

- Schematic assembly description

- Manufacturing Process Flow

- Cost analysis, step by step

- Manufacturing cost breakdown

- Selling price estimation

Key Topics Covered:

Glossary

Overview/Introduction

- Executive Summary

- Reverse Costing Methodology

Physical Analysis

- Synthesis of the Physical Analysis

- Physical Analysis Methodology

- Module Views & Dimensions

- Module Passive Components Assembly

- Module X-Ray

- Module Delamination -Layer 1

- Module Delamination -Layer 2

- Module Delamination -Embedded IC Die

- Module Delamination -Layer 3

- Module Delamination -Layer 4

- IC Die Views & Dimensions

- IC Die Markings

- IC Die Delayering

- IC Die Process

- Cross-section 1 Overview

- Cross-section 1 Details

- Cross-section 2 Overview

- Cross-section 2 Details

- Cross-section 3 Overview

- Cross-section 3 Details

Manufacturing Process Flow

- Global Overview

- IC Process Flow

- Description of the IC Wafer Fabrication Unit

- SESUB Packaging Process Flow

- Description of the Packaging Panel Fabrication

Cost Analysis

- Synthesis of the Cost Analysis

- Main Steps of Economic Analysis

- Yields Explanation

- Yields Hypotheses

- IC Front-End : Hypotheses

- IC Front-End Cost

- IC Back-End 0: Probe TestCost

- IC Back-End 0: RDL, Thinning & Dicing Cost

- IC Die Cost

- Back-End: Embedded Die Packaging Hypotheses

- Back-End: SESUB Panel Cost

- Back-End: SESUB Panel Cost per Process Steps

- Back-End: SESUB Panel Equipment Cost per Family

- Back-End: SESUB Panel Material Cost per Family

- Back-End: Packaging Price

- Back-End: Final Test

- SiPModule Cost

Estimated Price Analysis

For more information visit http://www.researchandmarkets.com/research/x3mcbx/rohm_dcdc_micro

Contacts

Research and Markets
Laura Wood, Senior Manager.
press@researchandmarkets.com
U.S. Fax: 646-607-1907
Fax (outside U.S.): +353-1-481-1716
Sector: Telecommunications and Networks

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Contacts

Research and Markets
Laura Wood, Senior Manager.
press@researchandmarkets.com
U.S. Fax: 646-607-1907
Fax (outside U.S.): +353-1-481-1716
Sector: Telecommunications and Networks