Chip Path Design Systems Announces Portals for Analysis and Selection of Advanced FPGA Devices

Vendor-neutral portals provide impartial ability to select devices from 28nm to 130nm

SAN FRANCISCO--(BUSINESS WIRE)--DESIGN AUTOMATION CONFERENCE--Chip Path™ Design Systems, the system-on-chip assembly company, today announced that it plans to deploy free web-accessible portals for selection of advanced FPGA devices from Altera Corp., Lattice Semiconductor Corp., Microsemi Corp. (Actel), and Xilinx Inc. implemented in technologies from 28nm to 130nm. Advanced tools also support new FPASSP devices that combine FPGA (field programmable gate arrays) with ASSP (application-specific standard product) subsystems, effectively competing with system-on-chip SoC/ASIC devices. Chip Path dubs these new devices FPASSP: field programmable ASSP.

“The entire semiconductor industry stands to gain from being able to use these devices with ever greater ease.”

“For the first time customers will have access to vendor-neutral tools that provide impartial ability to select FPGAs from the four major vendors,” said J. George Janac, CEO of Chip Path Design Systems. “As FPGAs have embraced the latest 28nm nodes much faster than ASICs or ASSPs, they have increasingly become a more competitive solution for box or systems designers.”

The Chip Path launch includes six portals for the analysis and selection of advanced FPGA and FPASSP devices. Two portals provide multi-vendor device selection. One of these two portals is purely for FPGA and the other for FPASSP. Four portals are individually dedicated to design with one of the four major vendors: Altera Corp., Lattice Semiconductor Corp., Microsemi Corp. (Actel), and Xilinx Inc.. Designers can enter resources or system-on-chip (SoC) architecture in their web-browser and see which devices will fit their design, the device costs, and other analyses. The portal spans 312 unique dies, over 8,000 packaged devices, and thousands of FPGA targeted intellectual properties (IPs).

Each Chip Path portal features three tools. First is an FPGA/FPASSP fitting tool based on resources. One simple form allows the entry of I/O, SERDES transceivers, LC or LUTs, memory, digital signal processors (DSPs), and embedded IP. With one click users see devices capable of fitting those resources, package configurations, speed grades, and pricing. The second tool is for the definition of SoC architecture based on Chip Path’s IP Directory catalog. Designers pick IP blocks and the tool analyzes devices capable of supporting their architecture. Finally, a third tool supports search for IP among the FPGA vendors and over 100 of their IP partners.

Since FPGA implementation density is typically much lower than that of SoC or ASIC (often over 22 times lower), vendors have begun a new trend of surrounding an SoC-style hard diffused CPU/memory subsystems with programmable FPGA fabric. Density of these CPU subsystems is as good as SoC, and the FPGA fabric provides extensibility. These new devices provide both low cost (as low as $15/device) and the ability to accommodate user logic. Chip Path tools are the first to support fitting and mapping to these devices.

The FPASSP trend first came with the Actel (now Microsemi) SmartFusion® devices based on the ARM Cortex™-M3 processor. This was quickly followed by the Xilinx® Zynq™ 7 and by Altera’s SoC FPGA in Cyclone® V and Arria® V, devices based on ARM Cortex™-A9. Chip Path’s ChipIPDirectory™ and architecture tools enable designers to select an entire subsystem or to use only a small portion of it. Architecture accommodates user logic and IP from vendors and their IP partners. What matters is the ability to fit the design’s architectural requirements and meet price targets. Chip Path has developed extensive cost modeling software and regularly mines device prices found on distributor websites.

“We are the world’s largest information aggregator for FPGA and FPASSP,” said Janac, “The entire semiconductor industry stands to gain from being able to use these devices with ever greater ease.”

Chip Path is making this methodology available on its website. Registered users can come to http://www.chippath.com . Various tools and portals can be accessed from its root. Subscription tools for advanced design are also available via credit card. In addition, tools will be on display at the Design Automation Conference (DAC) from June 4-7 in San Francisco, CA in Booth #306.

About Chip Path

Chip Path Design Systems is a privately funded company dedicated to system-on-chip (SoC) architectural assembly that merges design, electronic design automation, and semiconductor IP. Targeting the front-end process from specification through IP assembly to physical planning, Chip Path delivers tools based on semiconductor IP for creation of new designs/devices as well as using existing devices that span SoC, FPGA, FPASSP, and ASSP.

The company is headquartered in Cupertino, Calif. 95014. Telephone: [phone]. Email: [e-mail]. Website: www.ChipPath.com

ChipPath, RealArchitect, ChipRFQ, ChipPlatform, ChipPlanner, RFQCompiler, IPCompiler, PhysicalRTL, PhysicalIP FpgaIPDirectory, ChipIPDirectory, and SemantIC Design are trademarks of Chip Path Design Systems.