SEMATECH SPCC Conference Featuring New Approaches to III-V Materials

AUSTIN, Texas--(BUSINESS WIRE)--Advanced technologies for cleaning, measuring and processing new III-V semiconductor materials for volume wafer manufacturing will be featured at SEMATECH’s Surface Preparation and Cleaning Conference (SPCC), March 22-24, at the Sheraton Austin Hotel.

“Creative Collaboration: New Directions for Our Industry.”

This year’s annual SPCC will focus on particle removal, including next-generation materials, controlling processes to minimize impact on fragile device structures, non-damaging methods to remove resist, and new metrology approaches for measuring passivation and surface defects.

“As an industry, we’re confronting the limits of physics in using silicon for advanced devices, which is forcing us to look for new materials among the III-V semiconductors,” said Joel Barnett, SPCC chairman and Senior Member Technical Staff in SEMATECH’s Front End Processes (FEP) division. “This year’s conference focuses on current developments and roadmap challenges in advanced wafer and surface prep techniques for the 22 nm technology node and beyond.”

For more than 10 years, SPCC has brought together leading researchers from industry and academia to focus on challenges in advanced wafer and mask cleaning and surface preparation. The conference presents cutting-edge information designed to help the industry meet technical goals outlined in the International Technology Roadmap for Semiconductors.

On opening day, Jimmy Price, Member Technical Staff, will deliver an invited paper on FEP’s success in using second harmonic generation (SHG) to evaluate the effects of different surface cleans and passivation treatments on indium gallium arsenide (InGaAs), a promising III-V material. The ability to accurately characterize III-V surfaces and interfaces using SHG highlights the potential of this technique as an in-line metrology system suitable for InGaAs-based chip manufacturing. “We now have a non-invasive method that process and device engineers can rely on to monitor the quality of III-V surfaces and interfaces,” said Price. “We spent a year developing this application, and I will be explaining it in some detail.”

Other highlights of SPCC 2010 include the following:

• A keynote address by SEMATECH president and CEO Dan Armbrust, on “Creative Collaboration: New Directions for Our Industry.”
• A session addressing non-damaging wafer cleaning techniques, including wet laser shockwave, controllable collapsing bubbles, sonoluminescent signal, and controlled use of CO₂-gasified deionized water. An invited panel will discuss these and other methodologies for removing particles in next-generation materials, including InGaAs.
• Talks on reducing damage to new materials from chemical-mechanical polishing (CMP) and resist removal. CMP can directly affect gate yield and is becoming more important in low temperature devices, where resists must be removed carefully to avoid damage to new III-V devices.

SPCC is part of the SEMATECH Knowledge Series—unique opportunities to focus on accelerating solutions for critical challenges in the nanoelectronics industry. For more information and registration details for SPCC 2010: http://www.sematech.org/meetings/spcc/.

About SEMATECH:

For over 20 years, SEMATECH® (www.sematech.org), the international consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.