Anova’s Variation Analysis Software Included in TSMC Reference Flow 10.0

SANTA CLARA, Calif.--(BUSINESS WIRE)--Anova Solutions Inc (Anova), an EDA company focusing on timing and power variation analysis, announces its path-based transistor level statistic timing and power analysis software ChronoVA PA has been included in TSMC Reference Flow 10.0. The software is using Stochastic Analysis Process (S.A.P), Anova’s patent technology, to analyze circuit timing and leakage power variation at the transistor level. It is a fast and scalable Monte Carlo solution interfacing with commercial circuit simulators for quick SSTA path verification.

“Anova’s ChronoVA PA tool can help designers to quickly and accurately extract the critical path timing variability by using our statistical device model, and is an important addition to TSMC Reference Flow 10.0 targeting our most advanced process nodes”

The ChronoVA PA software brings transistor-level SPICE accuracy at 30 to 100 times faster than SPICE Monte Carlo timing simulation. The software was evaluated on various SSTA critical paths; the timing mean and sigma value results are less than 1% different in average compared with SPICE Monte Carlo.

“Anova’s ChronoVA PA tool can help designers to quickly and accurately extract the critical path timing variability by using our statistical device model, and is an important addition to TSMC Reference Flow 10.0 targeting our most advanced process nodes,” says Tom Quan, deputy director of Design Service Marketing at TSMC.

“Timing and leakage variations have been big concerns starting from 40nm designs, an accurate, fast and scalable analysis solution is necessary. S.A.P as the foundation of our variation analysis products has been implemented for both transistor level full customer circuits and cell-based SOC designs. The hierarchical S.A.P approach helps accurate variation prediction for the critical paths in their design. The software traces the critical path timing arcs and signal propagation automatically. By interfacing with commercial SPICE and STA tools, designers can easily analyze their critical path timing variability and use the results for validation and design sign-off. We are glad to work with TSMC’s team to qualify our software with TSMC device statistical models and be in the design reference flow 10.0,” said Jun Li, CEO of Anova Solutions Inc.

About Anova Solutions Inc.

ANOVA is an electronic design automation company offering fast library characterization and chip statistical static timing analysis software for semiconductor system on chip design. It has offices in Santa Clara, California, USA and a subsidiary in Yokohama City, Japan. For more information, visit http://www.anova-solutions.com