|Ocelot ZFP Leverages DFT to Collapse the Engineering to Production Timeline, Maximize Production Efficiency, and Enable Cost of Test to Scale with Moore's Law|
Inovys Corporation, the leader in the convergence of semiconductor design and test, introduced today the Ocelot ZFP, the industry's lowest cost semiconductor production test solution. The latest addition to the Inovys family of testers, the Ocelot ZFP (Zero Foot-Print) extends the Inovys platform reach from engineering, with the highly successful desktop Personal Ocelot, to high volume production of new generation semiconductor devices. The Ocelot ZFP combines the best elements of Design For Test (DFT) to reduce typical design debug from weeks to hours while providing the shortest path to high volume production. Architected around the IEEE1450 standard STIL (Standard Test Interface Language), the Ocelot ZFP is simple to use, has a short learning curve and enables customers to typically be productive within one day. This platform provides seamless bidirectional interfaces between ATE and EDA -- including the latest tools from Cadence, Mentor Graphics, Synopsys and others. The Ocelot ZFP successfully eliminates the design to test bottleneck, accelerating customer time to volume production.
Leveraging an optimal combination of structural and functional test to meet the requirements of multiple device generations, the Ocelot ZFP preserves capital investment while scaling with Moore's Law. The Ocelot ZFP also eliminates the time consuming and error prone translation process required by all proprietary test languages by enabling test programs that are automatically and immediately generated from the ATPG output of the EDA tools using native STIL. The Ocelot ZFP employs standard off-the-shelf components resulting in best-in-class system level reliability; more than 3X competitive platforms. In addition to lower acquisition and maintenance costs, the Ocelot ZFP has the lowest operating cost -- requiring no floor space and one tenth the power consumption of traditional test systems. The combination of these elements provides the lowest possible cost of test.
"Complex SoC (System on Chip) devices are getting harder to test due to increasing gate count and density, new technology nodes and new packaging methods," said Colin Ritchie, vice president of marketing, Inovys Corporation. "The arrival of SIP and other multi-chip packaging techniques often cause a decrease in external access and increase the creation of new fault mechanisms. Our customers needed a new test methodology to meet these challenges and to free them from the traditional tester treadmill. Our response is the Ocelot ZFP which is optimized for structural test. Structural testing of complex SoCs enables larger pattern memories, advanced failure data capture and analysis capabilities -- all of which traditional testers either lack or are too cost prohibitive. The Ocelot ZFP optimizes fault coverage resulting in maximum production efficiency and maximum yields."
Inovys Corporation will demonstrate the Ocelot ZFP during Semicon West week. Please visit www.inovys.com for more information.
About Inovys Corporation
Inovys Corporation is leading the revolution in semiconductor design and test convergence, providing customers with innovative test solutions for design debug, production and failure analysis. The Company provides integrated test systems for advanced System on Chip (SoC) devices used in computing, consumer and communication applications. Inovys provides a comprehensive test suite that enables semiconductor companies to reduce design debug from weeks to hours, lower production test costs by a factor of four and support real-time yield enhancements with unique failure analysis tools. Additional information is available at www.inovys.com.